Division in HLS doesn't work

[MAlek2]

I'm trying to write a simple matrix inversion program and the generate an HDL code from it.

I'm working with fixed point math. Here is a part of my code:

typedef ac_fixed<40, 20, true> fixed_40_20_t;   hls_register fixed_40_20_t matrix_A_src[8][16]; hls_register fixed_40_20_t matrix_A_temp_mult[16]; hls_register ac_fixed<60, 20, true> div_res; hls_register fixed_40_20_t numerator; hls_register fixed_40_20_t denominator;   for (int i = 0; i < 8; ++i) { #pragma unroll for (int p = 0; p < 16; ++p) { denomerator = matrix_A_src[i][i]; if(i == p) matrix_A_src[i][p] = 1; else { numerator = matrix_A_src[i][p]; div_res =numerator / denominator; matrix_A_src[i][p] = div_res; } } for (int k = 0; k < 8; ++k) { if(k != i) { for (int j = 0; j < 16; ++j) { matrix_A_temp_mult[j] = matrix_A_src[k][j] * matrix_A_src[i][j]; } #pragma unroll for (int j = 0; j < 16; ++j) { matrix_A_src[k][j] = matrix_A_src[k][j] - matrix_A_temp_mult[j]; } } } }

The problem is in division operator. It does not divide at all and after two cycles of division the program gives an exception and crushes. But if i change division to another operator, like multiply, all program works good.

In examples i could't find any example of fixed point division.

Also a simple code like this:

typedef ac_fixed<40, 20, true> fixed_40_20_t;   hls_register ac_fixed<60, 20, true> c; hls_register fixed_40_20_t a,b;   a = 123.456; b = 34.56;   c = a / b;   printf(" %f \n", c.to_double());

gives the answer

c = 3.572222 which is right

[KhaiChein_Y_Intel]

Hi,

I notice that you modified the message from gives the answer c = 3.572222 which is wrong to gives the answer c = 3.572222 which is right. Do you see the expected behavior?

We have one example for fixed point in <quartus_installation_directory>hls\examples\tutorials\ac_datatypes

Thanks.

[MAlek2]

Yes, with that code it was my mistake. But with the matrix calculations it was not. Anyway i played with that code and found out that placing string

denomerator = matrix_A_src[i][i];

inside of the loop was a bad idea. So when i moved that string outside of the loop i got my code work.

But than i stuck with another problem. I'm trying to compile generated code for Cyclone 10 GX and Quartus 17.1 completely stucks at analysis step. The error message says it is not enough memory for compiling this code. But as you can see the source code is very simple. I played with #pragma unroll and sometimes HDL code just can't be synthesized because it is too big for Cyclone 10 GX.

So my next question is how can i find out why does my code is synthesized in some wrong way leading to a very large area?

[KhaiChein_Y_Intel]

Hi,

What is the exact error message? Could you share the full error message?

Thanks

[MAlek2]

Here is the full message from the compilator:

make -k target-fpga-nosim time i++ test1.cpp -march="Cyclone10GX" -v --time time_fpga.out -ghdl --simulator none --clock 200MHz -o target-fpga-nosim Target FPGA part name: 10CX220YF780I5G Target FPGA family name: Cyclone10GX Target FPGA speed grade: -5 Analyzing test1.cpp for hardware generation Optimizing component(s) and generating Verilog files Compiler Error: The estimation for the area taken by this design far exceeds the size of the board. Compiler Error: If you wish to continue compilation anyways, use the flag "--dont-error-if-large-area-est". HLS Verilog code generation, llc FAILED. Command exited with non-zero status 1 27.54user 0.40system 0:31.79elapsed 87%CPU (0avgtext+0avgdata 343632maxresident)k Makefile:26: recipe for target 'target-fpga-nosim' failed 288912inputs+75928outputs (1158major+150067minor)pagefaults 0swaps make: *** [target-fpga-nosim] Error 1 "make -k target-fpga-nosim" terminated with exit code 2. Build might be incomplete.

[KhaiChein_Y_Intel]

Hi,

It seems like the design is too large to be fitted into the board. Have you tried to use the flag suggested?

Thanks

[KhaiChein_Y_Intel]

Hi, May I know if you have any updates? Thanks