FPGA Compile times out even with 24 hours

[itzmeanjan]

Hi,

Good day !

I'm using Intel SYCL/ DPC++ for targeting Intel Stratix 10 FPGA on Intel Devcloud, but my current design is somewhat large, so it's taking more time to compile the design. Even when I set `wall_time=24:00:00` in `qsub` command, it doesn't complete by that time.

Is it possible to anyhow set wall_time to higher time span ( say 48:00:00 ) ?

[itzmeanjan]

I just discovered this response, how can I submit job to FPGA queue ?

[aikeu]

Hi itzmeanjan,

Apologies for the delayed response. Due to previous holiday season we would require some time to run through the situation to understand further and will get back to you as soon as possible (approx. a week/two). Thank you for the patients.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi itzmeanjan,

This is the document link for FPGA queue submission:

https://devcloud.intel.com/oneapi/documentation/job-submission/

btw, I noticed that how to change job submission timeout in the document is still max at 24h.

Thanks.

Regards,

Aik Eu

[itzmeanjan]

Hi @aikeu ,

I've simplified my design such that h/w synthesis time doesn't exceed max walltime, so this is not a problem anymore. Thanks anyway.

Regards

[aikeu]

Hi itzmeanjan,

Good to know that you are able to simplify your design in order to get the compilation done within 24H.

I will close this thread for now.

Thanks.

Regards,

Aik Eu