Good day !
I'm using Intel SYCL/ DPC++ for targeting Intel Stratix 10 FPGA on Intel Devcloud, but my current design is somewhat large, so it's taking more time to compile the design. Even when I set `wall_time=24:00:00` in `qsub` command, it doesn't complete by that time.
Is it possible to anyhow set wall_time to higher time span ( say 48:00:00 ) ?
Apologies for the delayed response. Due to previous holiday season we would require some time to run through the situation to understand further and will get back to you as soon as possible (approx. a week/two). Thank you for the patients.
This is the document link for FPGA queue submission:
btw, I noticed that how to change job submission timeout in the document is still max at 24h.