HBM - high band memory

[ymiler]

Hi,

I tried to generate an HBM memory example module when my device is Stratix 10.

I have two projects:

1. One where the HBM is located at the top, and another where the HBM is located at the bottom.

Both projects are configured in the same way: only channel 0 (ch0) is used.

The project with the HBM located at the bottom works, and Quartus successfully completes all stages up to the "Generate Programming Files" stage.

However, the project with the HBM located at the top fails during the Plan stage, and I receive the following message:

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 UFIND4H_UIB(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 UFIND4H_UIB, which is within High Bandwidth Memory (HBM2) Interface Intel FPGA IP ed_synth_hbm_0_example_design_altera_hbm_1961_juniqfi.
Info(14596): Information about the failing component(s):
Info(175028): The UFIND4H_UIB name(s): hbm_0_example_design|hbm_0_example_design|uib|arch_inst|ufi_inst|ufi_inst
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between source HBMC and the UFIND4H_UIB
Info(175026): Source: HBMC hbm_0_example_design|hbm_0_example_design|uib|arch_inst|hbmc_inst|hbmc_inst
Info(175021): The source HBMC was placed in location HBMC_X95_Y2_N1
Error(175022): The UFIND4H_UIB could not be placed in any location to satisfy its connectivity requirements
Info(175029): 1 location affected
Info(175029): UFIND4HUIB_X95_Y292_N0

Could you assist how can I solve it ?

[AdzimZM_Intel]

Hi ymiler,

I have a few questions in points below:

• What is the device OPN that you used?
• Which Quartus version that you used?
• Are using example design that has been generated from the HBM2 IP?
  • For example, this document has provided some guides to create the example design: https://www.intel.com/content/www/us/en/docs/programmable/683379/20-1-19-4-0/generating-the-synthesizable-high-bandwidth-15038.html

Regards,

Adzim

[ymiler]

• What is the device OPN that you used?  -  stratix10 1SM21BHU2F53E2VG
• Which Quartus version that you used?   -  Quartus Prine version 22.3
• Are using example design that has been generated from the HBM2 IP?  - Yes 

[ymiler]

Attach the archive project

[AdzimZM_Intel]

Hi ymiller,

I think there are some missing files from your archive project that may cause the issue.

It's reporting there are conflict to constraint the design.

Can you start designing your project based on the design in the attachment?

This is the example design that can compile successfully.

Please check if you still see the failures with this design.

Regards,

Adzim

[ymiler]

Hi Adzim,

Then, I tried to create example design from scratch again ( HBM location -top )

but still I got error: 

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 UFIND4H_UIB(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 UFIND4H_UIB, which is within High Bandwidth Memory (HBM2) Interface Intel FPGA IP ed_synth_hbm_0_example_design_altera_hbm_1961_g23n22y.
Info(14596): Information about the failing component(s):
Info(175028): The UFIND4H_UIB name(s): hbm_0_example_design|hbm_0_example_design|uib|arch_inst|ufi_inst|ufi_inst
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between source HBMC and the UFIND4H_UIB
Info(175026): Source: HBMC hbm_0_example_design|hbm_0_example_design|uib|arch_inst|hbmc_inst|hbmc_inst
Info(175021): The source HBMC was placed in location HBMC_X95_Y2_N1
Error(175022): The UFIND4H_UIB could not be placed in any location to satisfy its connectivity requirements
Info(175029): 1 location affected
Info(175029): UFIND4HUIB_X95_Y292_N0

Just want to remind that when the HBM location define in the Bottom everything works correctly 

Do you have idea how can I solve it ?

[ymiler]

want to add to my previous post :

your archive project works fine and compile successfully in my workspace ,

but when I try to create from scratch example design ( HBM location -top ) still I get error

[ymiler]

Hi 

good news!!

I found the root cause of the error  :

Error(175001): The Fitter cannot place 1 UFIND4H_UIB, which is within High Bandwidth Memory (HBM2) Interface Intel FPGA IP ed_synth_hbm_0_example_design_altera_hbm_1961_g23n22y

It was my set_location_assignment pin clock to PIN_AR26 - when remove it the Quartus succeed to finish the Plan stage successfully

But , Why ? this is legal pin ?

In addition , when the HBM is located at the bottom  there is no issue even the assignment of the PIN_AR26

Are there more problematic pins when the HBM locate at the top ?

[ymiler]

Hi 

I found the issue 

the solution is here :

Place this reference clock input on the UIB_PLL_REF_CLK_00 pins while using the HBM2 device on the bottom of the FPGA, or the UIB_PLL_REF_CLK_01 pins while using the HBM2 on the top of the FPGA.

when I locate the right pin it works