HLS support in Lite 19.1

[SParv4]

HLS is not available in the Additional Software tab, though the landing page for HLS :

https://www.intel.in/content/www/in/en/software/programmable/quartus-prime/hls-compiler.html?erpm_id=9341628

says HLS is supported by the Quartus Prime Pro Edition, Quartus Prime Standard Edition, and Quartus Prime Lite Edition

Is HLS supported in Lite for Cyclone 10 family? Because Xylinx seems to give an HLS compiler for their entry level FPGAs

[MEIYAN_L_Intel]

Hi,

I had tried to install the Quartus Prime Lite v19.1 and I could not found the HLS compiler included in the Quartus Prime software package.

I am still clarify the information internally.

The Cyclone 10 LP family device is supported in Quartus Prime Lite v19.1 as stated in the link below:

https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html

Thanks

[MEIYAN_L_Intel]

Hi,

I had installed Quartus Prime Lite v19.1 (window version) and Quartus Prime Lite v18.1 (window version).

In Quartus Prime Lite v19.1, there is no HLS directory installed.

But in Quartus Prime Lite v18.1, there is a HLS directory installed.

Could you try to install Quartus Prime Lite v18.1 with Cyclone 10 LP device supported and shown in link below:

https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html

Thanks

[SParv4]

Hi, I tried 19.4 Pro with Cyclone 10 GX. This is my user feedback.

1. Like AHDL, Verilog or Schematic, I should be able to enter my design in Quartus GUI itself using C/C++. (Well Quarts GUI itself has become old and requires renovation, e.g can use Direct 3D for RTL viewer, Pin Planner etc. Even android game have better user responsiveness)
2. It should produce RTL logic as the above mentioned design files produce.
3. Right now HLS compiles very slowly, produces so many files and the output is cluttered, that coding in AHDL or Verilog is easier.

I think HLS is not yet an alternate for the traditional design entry methods, but might soon become one.

[MEIYAN_L_Intel]

Hi,

Thanks you for your information and feedback. I will report this to the developer.

According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls.pdf, Intel HLS compiler compiles the design to an x86-64 object or FPGA-targeted RTL code, and creates an executable testbench.

After compilation in HLS, you may saw the HDL file in component directory.

Also, you can use the command "eg:  i++ --quartus-compile --simulator none -march=CycloneV counter.cpp -o test-fpga -v" and the results and files will be put in .prj/quartus directory.

For you information, the HLS compiler Lite v19.1 can be download as standalone software from https://fpgasoftware.intel.com/19.1/?edition=lite

Thanks

[SParv4]

Hi,

Thanks for uploading the HLS compiler Lite v19.1. I will give it a try with Cyclone10LP

I will also try  i++ --quartus-compile.

For counter.cpp the quaruts_compile.sv file generated looks good.

But for ''interp_decim_filter'' example the .sv file does not seem complete and instead links to a plethora of other component files?

That is not a problem as long as I can get .bdf or .ini (AHDL) file which I can use in my project without going through the Platform Designer.

[MEIYAN_L_Intel]

Hi, 

For your information, if you would like to add the generated IP into Platform Designer, you can refer to chapter 8.2 as document below: 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-std.pdf

May I know which .sv file seem not complete as you mentioned earlier?

Thanks

[SParv4]

Hi,

The following is the output from the command prompt:

========================

E:\intelFPGA_pro\19.4\hls\examples\image_downsample>i++ --quartus-compile --simulator none -march=Cyclone10GX bmp_tools.cpp main.cpp resize.cpp -o test-fpga -v

Target FPGA part name:  10CX220YF780I5G

Target FPGA family name: Cyclone10GX

Target FPGA speed grade: -5

Analyzing bmp_tools.cpp for hardware generation

Analyzing main.cpp for hardware generation

Analyzing resize.cpp for hardware generation

Optimizing component(s) and generating Verilog files

aocl-opt.exe takes CPU load of 25% for 2 hrs

How long will it take to generate??

[SParv4]

I tried this simple adder

#include "HLS/hls.h"   #ifndef __INTELFPGA_COMPILER__ #include "ref/ac_int.h" #else #include "HLS/ac_int.h" #endif     component uint8 s_adder(uint8 a, uint8 b) { return (a + b); }

and got the attached RTL.

The compile time , the convenience and finally the RTL generated is not satisfactory for at least simple systems.

I will continue with IP catalog and AHDL.

[MEIYAN_L_Intel]

Hi,

Thank you for your information. I had reported to developer for this RTL generated with simple adder system.

Thanks