Help with AOCL_LINK_CONFIG not finding OpenCL.lib

[CMull14]

Hi, I could really use some help on this.

Preface: My target board is a Altera Terasic DE5-Net and I have successfully compiled a hello_world test from them through similar means. This leads me to believe that my Environment Variables, BSP, and OpenCL are setup and configured correctly. My host machine is running Windows 10 with version 19.1 of Quartus Standard.

Problem: I am attempting to make a Project with the attached Make File. Upon running make I get the following error.

g++: error: /libpath:C:/intelFPGA/19.1/hld/host/windows64/lib: No such file or directory

g++: error: OpenCL.lib: No such file or directory

make: *** [Makefile:169: run.exe] Error 1

My initial thought was that it couldn't find the directory or lib because of the appended /libpath: at the front of the location, but further reading into the documentation at https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807965224.html#ewa1411400813347 leads me to believe that it is correctly appending /libpath: to the front.

The OpenCL.lib file is at the location listed. In the Make File, I find that the actually setup for this command is at

LINK_CONFIG = $(shell aocl link-config ) 

and the call at

.PHONY: all all: host fpga   .PHONY: host host: $(HOST_EXE)   .PHONY: fpga fpga: $(DEV_EXE)   $(HOST_EXE): $(HOST_OBJS) $(CXX) $(OCV_LIBDIRS) $(OCV_INCLUDES) $(HOST_OBJS) -o $@ $(LINK_CONFIG) $(OCV_LIBS) %.o: %.cpp $(CXX) $(OCV_LIBDIRS) $(OCV_INCLUDES) $(CXXFLAGS) -c $< -o $@ $(COMP_CONFIG) $(OCV_LIBS)   $(DEV_EXE): $(KERNEL_SRCS) $(OCC) $(OCCFLAGS) $< -o $@

I will also paste the entire make file below. Any help is appreciated, thanks!

#set source and target for host HOST_EXE = run.exe HOST_SRCS = ./host/main.cpp ../common/ocl_util.cpp ../common/timer.cpp HOST_OBJS = $(HOST_SRCS:%.cpp=%.o) HOST_INCS = ../common HOST_DEBUG = 1   #choose the BSP you would like to use #BSP_DIR = /home/fpga/intelFPGA_pro/19.1/hld/board/a10_ref #BSP_DIR = /home/fpga/intelFPGA_pro/19.3/hld/board/a10_ref #BSP_DIR = /home/fpga/intelFPGA_pro/BSP/de5a_net_ddr4 BSP_DIR = C:\intelFPGA\19.1\hld\board\terasic\de5net #BSP_DIR = /home/fpga/intelFPGA_pro/BSP/f10a_bsp_181/bsp_1801/f10a_remote_bsp   #if you are loading images from OpenCV interfaces please set to 1 USE_OPENCV = 0   #set source and target for device #supported vendors are xilinx, altera, amd VENDOR = altera #select the host archecture x86|arm32 PLATFORM = x86 #optional flows are hw|hw_emu|sw_emu|report|profile|rtl|hw_sim #hw -> generate hw for deployment #hw_emu -> generate waveform for SDAccel #sw_emu -> perform software emulation #hw_sim -> co-sim with Modelsim for Intel OpenCL SDK #report -> generate aoco and report(only for std version) for fast evaluation #rtl -> generate aocr and report(only for pro version) for fast evaluation #profile -> insert performance counters in fpga for dynamic profiling #init -> initialization for incremental hw compilation with reduced time #fast -> fast incremental compilation with reduced time FLOW = rtl #select which kernel file is used ifeq ($(VENDOR),xilinx) KERNEL_SRCS = ./device/conv_pipe_xilinx.cl else KERNEL_SRCS = ./device/conv_pipe.cl endif KERNEL_NAME = conv KERNEL_DEFS = KERNEL_INCS = KERNEL_DEBUG = 1 #additional pragma for xilinx CU_NUM = 1 MAX_MEM_PORT = 0 MEM_PORT_SIZE = 512   #select the device binary name ifeq ($(VENDOR),xilinx) DEV_EXE = $(KERNEL_NAME).xclbin else ifeq ($(VENDOR),altera) ifeq ($(FLOW),report) DEV_EXE = $(KERNEL_NAME).aoco else ifeq ($(FLOW),rtl) DEV_EXE = $(KERNEL_NAME).aocr else DEV_EXE = $(KERNEL_NAME).aocx endif else ifeq ($(VENDOR),amd) DEV_EXE = endif   #host compiler options CROSS-COMPILE = arm-linux-gnueabihf- ifeq ($(PLATFORM),x86) CXX := g++ ifeq ($(USE_OPENCV),1) #add your OpenCV PATH here OCV_INCLUDES = C:\intelFPGA\19.1\hld\host\include OCV_LIBDIRS = C:\intelFPGA\19.1\hld\host\windows64\lib #for opencv_2.x #OCV_LIBS = -lopencv_core -lopencv_imgproc -lopencv_highgui -lopencv_ml #for opencv_3.x OCV_LIBS = -lopencv_core -lopencv_imgcodecs -lopencv_imgproc -lopencv_highgui -lopencv_ml endif else ifeq ($(PLATFORM),arm32) CXX := $(CROSS-COMPILE)g++ ifeq ($(USE_OPENCV),1) #add your cross compile OpenCV PATH here OCV_INCLUDES = -I/usr/local/opencv-arm/include/ OCV_LIBDIRS = -L/usr/local/opencv-arm/lib OCV_LIBS = -lopencv_core -lopencv_imgproc -lopencv_highgui -lopencv_ml endif endif   #select whether use OpenCV or not ifeq ($(USE_OPENCV),1) CXXFLAGS = -g -Wall -std=c++11 -DUSE_OPENCV else CXXFLAGS = -g -Wall -std=c++11 endif   #select compile for sw_emu or hw (used verion >= 19.3) ifeq ($(FLOW),sw_emu) CXXFLAGS += -DSW_EMU endif   ifeq ($(VENDOR),xilinx) COMP_CONFIG = -I$(XILINX_SDX)/runtime/include/1_2 -I$(HOST_INCS) -DFPGA_DEVICE -DXILINX LINK_CONFIG = -L$(XILINX_SDX)/runtime/lib/x86_64 -lxilinxopencl else ifeq ($(VENDOR),altera) COMP_CONFIG = $(shell aocl compile-config ) -I$(HOST_INCS) -DFPGA_DEVICE -D_WIN32 LINK_CONFIG = $(shell aocl link-config ) else ifeq ($(VENDOR),amd) DEV_EXE = endif   #opencl compiler options #xilinx ifeq ($(VENDOR),xilinx) OCC = $(XILINX_SDX)/bin/xocc -DXILINX OCCFLAGS = --platform xilinx:kcu1500:4ddr-xpr:4.0 -t $(FLOW) -O2 --kernel_frequency 200 --save-temps --report system \ --memory_port_data_width memWrite:32 \ --memory_port_data_width memRead:512 \ --nk memWrite:1 --nk coreConv:1 --nk lrn:1 --nk maxPool:1 --nk memRead:1 \ #memory optimization for xilinx ifeq ($(MAX_MEM_PORT), 1) OCCFLAGS += --max_memory_ports all OCCFLAGS += --memory_port_data_width all:$(MEM_PORT_SIZE) endif #altera else ifeq ($(VENDOR),altera) OCC = aoc ifeq ($(FLOW),sw_emu) OCCFLAGS = -v -report -march=emulator -emulator-channel-depth-model=strict -I device/RTL -L device/RTL -l rtl_lib.aoclib -board-package=$(BSP_DIR) else ifeq ($(FLOW),hw) OCCFLAGS = -v -report -seed=3 -I device/RTL -L device/RTL -l rtl_lib.aoclib -board-package=$(BSP_DIR) else ifeq ($(FLOW),init) OCCFLAGS = -v -report -seed=3 -incremental -I device/RTL -L device/RTL -l rtl_lib.aoclib -board-package=$(BSP_DIR) else ifeq ($(FLOW),fast) OCCFLAGS = -v -report -seed=3 -incremental -fast-compile -I device/RTL -L device/RTL -l rtl_lib.aoclib -board-package=$(BSP_DIR) else ifeq ($(FLOW),profile) OCCFLAGS = -v -report -profile -I device/RTL -L device/RTL -l rtl_lib.aoclib -board-package=$(BSP_DIR) else ifeq ($(FLOW),report) OCCFLAGS = -v -c -report -I device/RTL -L device/RTL -l rtl_lib.aoclib -board-package=$(BSP_DIR) else ifeq ($(FLOW),rtl) OCCFLAGS = -v -rtl -report -fmax=300 -I device/RTL -L device/RTL -l rtl_lib.aoclib -board-package=$(BSP_DIR) else ifeq ($(FLOW),hw_sim) OCCFLAGS = -v -report -march=simulator -ghdl -I device/RTL -L device/RTL -l rtl_lib.aoclib -board-package=$(BSP_DIR) endif # misc options for altera # add support for arbitrary precision integers OCCFLAGS += -I $(INTELFPGAOCLSDKROOT)/include/kernel_headers #amd else ifeq ($(VENDOR),amd) OCC = OCCFLAGS = endif   #debug option ifeq ($(KERNEL_DEBUG),1) OCCFLAGS += -g else OCCFLAGS += -g0 endif   .PHONY: all all: host fpga   .PHONY: host host: $(HOST_EXE)   .PHONY: fpga fpga: $(DEV_EXE)   $(HOST_EXE): $(HOST_OBJS) $(CXX) $(OCV_LIBDIRS) $(OCV_INCLUDES) $(HOST_OBJS) -o $@ $(LINK_CONFIG) $(OCV_LIBS) %.o: %.cpp $(CXX) $(OCV_LIBDIRS) $(OCV_INCLUDES) $(CXXFLAGS) -c $< -o $@ $(COMP_CONFIG) $(OCV_LIBS)   $(DEV_EXE): $(KERNEL_SRCS) $(OCC) $(OCCFLAGS) $< -o $@   .PHONY: run run: ./run.exe $(KERNEL_NAME).aocx   .PHONY: log log: ./run.exe $(KERNEL_NAME).aocx | tee >run.log   .PHONY: clean clean: rm -rf *.sof *.xclbin *.rpt *.sv *.efisim *.tmp *.temp *.txt *.json *.dir *.aocx *.aoco *.aocr *.source *.exe xocc* sdaccel* ./device/*.ll ./host/*.o ../common/*.o *.jou *.mon *.cl

[AnilErinch_A_Intel]

Hi

Please let us know , whether the suggestions in the below forum post helps you.

https://forums.intel.com/s/question/0D50P00003yyRHkSAM/build-issue-with-eds

Thanks and Regards

Anil