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Hi Nadia,
I had found out that an op-amp implement using FPGA by including ADC or DAC device in your design.
The link below shows an example of ADC design in MAX 10 device:
https://www.youtube.com/watch?v=0oO1RFa-4Xk
If the IP of ADC in Quartus is not suitable for the FPGA board, a design is required for the IP of ADC in Quartus.
Thanks.

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