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Beginner
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Host channels arria 10 pac [DevCloud]

Hi,

 

I am interested in work with the Intel host pipes in Arria10 FPGA, that is available in the a10gx_hostpipe bsp. In the Intel DevCloud I only see the a10_pac, which does not have channels. Is it possible to get access to a bsp with that feature?

Thanks in advance

 

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Moderator
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Which nodes you are trying to access?

You might access to the wrong nodes for it, try to look for Intel® Arria® 10 GX FPGA Development Kit nodes.

You may check this https://github.com/intel/FPGA-Devcloud/tree/master/main/Devcloud_Access_Instructions#devcloud-access.... If the nodes is not there, I will request them to setup one for it.

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Beginner
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Thanks, Kenny_t for your answer, The documentation link only refers to Arria10 PAC, as my devcloud_login. Currently, I am using the node s005-n004. I've tried to list the available nodes but I can't differentiate between arria GX and PAC devices .The "properties" don't make a difference, it just shows arria10. I accessed a couple of them, and all are PAC devices. how I can identify an arria10GX node? El vie., 19 jun. 2020 a las 6:14, Intel Forums (<supportreplies@intel.com>) escribió:
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Novice
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I am also trying to setup host pipes and would very much appreciate it if there was a node that supported it.

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Beginner
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I am in a similar situation. Trying to compile the example kernel from the loopback host pipe example on Arria 10 nodes (137-139)

I get the same error as discussed in an older forum post.

https://forums.intel.com/s/question/0D50P00003yyTKHSA2/aoc-compile-error-using-host-channel-feature?...

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Novice
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Same here. I am very interested getting OpenCL host pipes working with our application. BTW I tried to get access to "right Arria 10 cloud" and got yet another DevCloud account w/o GUI tools and Tcl scripts.

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I'm curious what application you want to run on the Arria 10 GX board that the A10 PAC cannot support? We can investigate installing that board, but it could take a month or longer as we need another server blade - all are occupied with PAC boards.

Thanks

Larry

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Novice
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Why just not to add Software support for host pipes to Intel PAC card?  This should be less than a month, it is just a software update! 

Our application is confidential at the moment. However, the convenience of pumping data via host channels has advantage of having much less code than handling ping-pong buffers with events, etc. And we all for less code and conveniences, correct?

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Beginner
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@Lawrence_L_Intel Hi Larry,

I am trying to use the host pipe example from https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/desig...

On the host side,  the application makes use  clMapHostPipeIntelFPGA API via function pointers.

map_pipe_fn = (void * (*) (cl_mem, cl_map_flags, size_t, size_t *, cl_int *)) clGetExtensionFunctionAddress("clMapHostPipeIntelFPGA");
unmap_pipe_fn = (cl_int (*) (cl_mem, void *, size_t, size_t *)) clGetExtensionFunctionAddress("clUnmapHostPipeIntelFPGA");

 The kernel arguments in the kernel are as follows:

#pragma OPENCL EXTENSION cl_intel_fpga_host_pipe : enable

__kernel void loopback_hostpipe( __attribute__((intel_host_accessible, blocking)) __read_only pipe ulong4 host_in,
                                 __attribute__((intel_host_accessible, blocking)) __write_only pipe ulong4 device_out,
                                 ulong length,
                                 uint nostop )
{ 
//kernel logic....
}

 

The requirements mentioned in the link I shared are

  • Intel® FPGA software v17.1 or later
  •  Intel FPGA SDK for OpenCL v17.1 or later
  • On Linux: GNU Make and gcc
  • On Windows: Microsoft Visual Studio 2010
  • Arria 10 PCIE Gen3x8 with target device as a10gx_hostch
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Beginner
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@Lawrence_L_Intel 

This is the summary of my attempts to compile the same example on Devcloud nodes.

On the Arria 10 PAC Compilation and Programming - RTL AFU, OpenCL node(S001-n139):

(Error while compiling the kernel)

 

aoc: Running OpenCL parser....
warning: unknown OpenCL extension 'cl_intel_fpga_host_pipe' - ignoring
#pragma OPENCL EXTENSION cl_intel_fpga_host_pipe : enable
                         ^
warning: expression result unused
    read_pipe(host_in, &data);
    ^~~~~~~~~~~~~~~~~~~~~~~~~
warning: expression result unused
    write_pipe(device_out, &data);
    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3 warnings generated.
aoc: Optimizing and doing static analysis of code...
Error: Channel has no point connection: ID= host_to_dev
  avm_channel_id_host_to_dev_read connection missing, or optimized away
Error: Could not write system script to file. System generation aborted!
Error: System integrator FAILED.

 

The host  code compiles without any errors. 

On the Stratix 10 PAC Compilation and Programming - RTL AFU, OpenCL node(S005-n008): 

(Error while compiling the host)

 

host/src/main.cpp:133:12: error: ‘clCreatePipe’ was not declared in this scope
     &status);

 

While I am using this example to get familiar with the host pipes, In our lab, we intend to use host pipes in applications where streaming of data from CPU-> FPGA can take place. We could simply transfer the data before invoking the kernels, but we are interested in evaluating the performance of this streaming approach (overlapping CPU->FPGA data transfer with kernel execution) 

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We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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