How can I implement the 'counter sample' in FPGA (DE10-Standard)?

[ishikawa]

I was able to high-level synthesize the counter in the hls example file, but I don't know how to implement it in the FPGA from there.

I have several files generated by high-level synthesis, which files can I use and how can I implement them in my FPGA using QuartusPrime?

[KennyTan_Altera]

Hi,

You may look into https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls.pdf -> 8. Integrating your IP into a System . Make sure you take a look into the previous secssion in case you missed out some steps.

You may also look into https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-started.pdf for I++ example

Thanks

[KennyTan_Altera]

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