How can I implement the 'counter sample' in FPGA (DE10-Standard)?

[ishikawa]

I was able to high-level synthesize the counter in the hls example file, but I don't know how to implement it in the FPGA from there.

I have several files generated by high-level synthesis, which files can I use and how can I implement them in my FPGA using QuartusPrime?

[Kenny_Tan]

Hi,

You may look into https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls.pdf -> 8. Integrating your IP into a System . Make sure you take a look into the previous secssion in case you missed out some steps.

You may also look into https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-started.pdf for I++ example

Thanks

[Kenny_Tan]

Since this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.