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How to set massive data read/write between HPS and FPGA ?

CAlex
New Contributor II
977 Views

Hi

Im using cycloneVsoc (BareMetal) and trying to transfer a massive amount of data from HPS to FPGA.

The thing is : if I use alt_write_xxxx() to transfer the data, there will be a big gap(around 2~3us) between two "write" orders.

 

I heard of burst write in avalon mm bridge but I didnt find any HWLIB support for that function.

The FPGA through SDRAM seems to be slower than the direct transfer.

 

So I want to know is there a way to read/write a massive data in a short period?

And How to do it.

 

Thank you 

 

Reguards

Alex

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mabdrahi
Employee
965 Views

Hi


I will check and investigate is there a way to read/write a massive data in a short

period


Stay tune


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mabdrahi
Employee
913 Views

Hi,


after i investigate, unfortunately data can not come as a stream. It must be put to SDRAM


to do that the DMA maybe involve. This example is probably worth looking at, it's a bare metal program but it give you an idea what has to happen at a low level to communicate with the DMA core: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html


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CAlex
New Contributor II
907 Views

Thank you,I'll check it later.

 

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mabdrahi
Employee
887 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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