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441 Discussions

How to use pac_a10 with Intel FPGA SDK for OpenCL 19.2?

HKim27
New Contributor I
530 Views

Hi, all.

I use Intel® Acceleration Stack Version 1.2 with Intel® Programmable Acceleration Card with Intel Arria® 10 GX FPGA on CentOS Linux release 7.2.1511.

Intel® Acceleration Stack Version 1.2 includes Intel FPGA SDK for OpenCL 17.1.1 and board support package for pac_a10, which works very well.

 

I try to use Intel FPGA SDK for OpenCL 19.2 with the board, to see if there is any performance improvement. Although board_env.xml indicates that the board support package is intended for Quartus 17.1, I try to include it from 19.2 with env var AOCL_BOARD_PACKAGE_ROOT.

 

However, the following error occurs. I also attached the full log.

Error (16045): Instance "ccip_std_afu|bsp_logic_inst|board_inst" instantiates undefined entity "board" File: /scratch/heehoon/polybench-gpu-1.0-mini/OpenCL/2DCONV/2DConvolution.cl_workspace_aocl19-multi/__all___workspace/ndi1_workspace_19/kernel0/build/bsp_logic.sv Line: 133 Error (16185): Can't elaborate user hierarchy "ccip_std_afu|bsp_logic_inst|board_inst" File: /scratch/heehoon/polybench-gpu-1.0-mini/OpenCL/2DCONV/2DConvolution.cl_workspace_aocl19-multi/__all___workspace/ndi1_workspace_19/kernel0/build/bsp_logic.sv Line: 133 Error (16185): Can't elaborate user hierarchy "ccip_std_afu|bsp_logic_inst" File: /scratch/heehoon/polybench-gpu-1.0-mini/OpenCL/2DCONV/2DConvolution.cl_workspace_aocl19-multi/__all___workspace/ndi1_workspace_19/kernel0/build/BBB_cci_mpf/hw/rtl/cci-mpf-if/cci_mpf_if.vh Line: 38

 

Quartus cannot find board entity, which is strange, since board/synth/board.v contains the board module when I check the build directory.

 

Is this expected behaviour? Can't I use board support package for 17.1.1 with Quartus 19.2?

 

Thanks in advance.

 

0 Kudos
7 Replies
HRZ
Valued Contributor II
186 Views

You cannot get the older BSP to work with newer versions of the compiler like that. Apparently the 19.x versions of the compiler are backward compatible with the BSP shipped with Intel Acceleration Stack v1.2. To enable the backward compatibility, follow the instructions in Section 3.5.1 of this document:

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_getting_...

 

However, many features added in the newer versions of the compiler require a BSP compatible with that version, and such features will not be available with backward compatibility.

MEIYAN_L_Intel
Employee
186 Views

Hi,

On top of that you can refer to https://www.intel.com/content/www/us/en/programmable/documentation/iyu1522005567196.html in chapter 2.4 shows the OpenCL software with 17.1.1.

Please note that you can used Intel FPGA SDK for OpenCL with two version higher than BSP.

Thanks

 

PSath2
Beginner
186 Views

Mylee, I am trying to find a solution to the same problem on the Intel DevCloud: (see post https://software.intel.com/en-us/forums/intel-devcloud/topic/832012). It also has the 17.1 pac_a10 BSP, but only the 18.1, 19.2, and 19.3 compiler stacks. (An Intel forum representative explicitly asked me to post in this forum. Since the OP and I have the same issue it felt most appropriate to tag on to this thread, but I can create a new post if necessary.)

 

The document you linked is not numbered by chapter so I am not following where 17.1 is listed as a hard requirement for OpenCL compilation. Can you provide a direct link to the relevant section? Is OpenCL support for the pac_a10 frozen at 17.1 (now two-years out of date)?

Maurizio_P_Intel
Employee
186 Views

Hi all.

The OpenCL BSP for Arria 10 PAC is bound to the Quartus Prime release 17.1.1 version released with the development stack. To use it with newer versions of the OpenCL compiler, the following environment variables need to be defined:

ACL_ACDS_VERSION_OVERRIDE=17.1.1

QUARTUS_ROOTDIR_OVERRIDE=<inteldevstack_root>/intelFPGA_pro

 

If you don't define the above variables, the OpenCL SDK will use the Quartus prime release aligned with its own - the posted log clearly shows Quartus Prime 19.2 is being used.

 

Note that the same applies for D5005 , where ACL_ACDS_VERSION_OVERRIDE must be set to 18.1.2

PSath2
Beginner
186 Views

Thanks, I gave it a try on the devcloud (node s001-n137) and it didn't help.

 

I haven't seen that particular environment variable before (ACL_ACDS_VERSION_OVERRIDE) and neither has Google, is there a list of these overrides somewhere in the documentation that I may have missed?

Maurizio_P_Intel
Employee
186 Views

I just checked n137 to n139. I noticed they only feature the DCP 1.2 RTE stack, that does not include Quartus Prime (so the assignment to QUARTUS_ROOTDIR_OVERRIDE points to nowhere in your case). I have now asked the platform owner to get this fixed

 

PSath2
Beginner
186 Views

Ahh, I have been using QUARTUS_ROOTDIR_OVERRIDE=/glob/development-tools/versions/intelFPGA_pro/18.1/quartus (or the 19.2/19.3) directories when I have been testing. (I am coming from a GPU OpenCL background and trying to add FPGAs to our wheelhouse, so I'm not the most familiar with the different editions of the Intel tools.)

 

Thanks for the escalation!

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