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Intel HLS (20.2) - problem with compiling more than 2 inputs writing into 1 output (one at time)


Generic functionality of component splitter, which can be seen in the attached picture.

Basic functionality of the request part:

  • Read mi32_in input and forwards it (based on address) to the right output.
  • If a request is READ, the request part writes address into ext_addr_fifo and starts response part.
    If a request is READ and into another external block then before (i.e. first there was READ request into external 1, then into external 2), request part is stopped and waits for completion of all responses.

Basic functionality of the response part:

  • Waits, until it started from the request part.
  • Reads ext_addr_fifo and reads from extern block based on the address and writes to output.


Two connections to external blocks (splitter folder)
With two external block connections, there is not a single problem with implementation and functionality.

More connections to external blocks (splitter_4con folder)

With more connections (I tested 3, 4 and splitter_4con folder represents 4 connections) to external blocks, there are problems with implementation.

The code is quite similar - only streams and cases added, but the request part does not give any output on mi32_out when co-simulation is made. I added some debug streams to see if the address is passed properly and it is. I tried two changes that helped, but with those, the design functionality is lacking:

  • Deleting condition if (success) on line 188 - output is given
  • Removing ext_addr_fifo and implementing address (addr from request part) into response part - output is given

Let's get to the strangest thing. As I was sure my description of the design is right, I tried to make more spaces between line 186 and 188. Strangely, after co-simulation, first 7 outputs were given (from 17).


So. Where can the problem be?

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3 Replies

I have just discovered that frequency plays important role in case of splitter with more than 2 connections. Basic frequency I used is 100 MHz and component properly works at 10 MHz. But the goal is at least 250 MHz. If you have any advice about better fmax, I will be happy to hear it.

Still, it doesn't answer why more spaces in code between line 186 and 188 helps.


Hi , 

Please find the fixed code attached. 

Thanks and Regards



Hi ,

Thanks for the observation. This is due to a known bug , fix of which is part of the next release.

You can fix this by forcing the component to II=1 using the hls_component_ii(1) attribute.

Attaching the modified file for your reference which is working.

Thanks and Regards