Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
676 Discussions

Manual simulation IP authoring

DorianL
Novice
358 Views

Hi everyone,

 

I wanted to know if this is possible to simulate manually an IP created by oneAPI and to create our own testbench instead of using the testbench created in the host file. Do I need to call the module in the file kernel_sys.v generated during a make report ? Thank you !

 

DorianL

0 Kudos
4 Replies
aikeu
Employee
264 Views

Hi DorianL,


I think can refer to the simulation topic from this document:

https://www.intel.com/content/www/us/en/docs/oneapi/programming-guide/2023-2/evaluate-your-kernel-through-simulation.html


Thanks.

Regards,

Aik Eu


0 Kudos
aikeu
Employee
235 Views

Hi DorianL,


I will close the thread if no further question.


Thanks.

Regards,

Aik Eu


0 Kudos
aikeu
Employee
179 Views

Hi DorianL,


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thanks.

Regards,

Aik Eu


0 Kudos
whitepau
Employee
114 Views

You can simulate oneAPI IP without the co simulation testbench. Please refer to the niosv code sample. 
https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/ReferenceDesigns/niosv

 

For smaller testbench it's also possible but you need to compile each of the files listed in the hw.tcl file. 

NOTE Make sure you are using Questa FE or Questa FSE, which come with all the altera libraries pre-compiled.

0 Kudos
Reply