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Does openCL map gate level operations to FPGA logic? There seems to be no 1-bit data types at the moment.
It will interesting to see bitwise operations to support for effective implmentation XNOR-neural-networks.
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You can probably use the "bool" datatype or use "char" and mask out the unnecessary bits. Though this could result in some extra area overhead compared to a pure HDL design depending on how smart the compiler/mapper is in handling the operations.
