I`m testing an HLS component with two explicit streaming interfaces. First interface is input and second is output. Component`s body incorporates if-else statement, and positive branch has computational latency of 36 clocks when I compile it alone.. Negative branch has computational latency of 0 clocks when I compile it alone.
When I compile entire component I expect to get variable latency based on what condition has been triggered in if-else statement by the input stream. But I always get latency of 36 cycles.
Is it possible to get variable latency for HLS streaming interfaces?
Due to the pipelined nature of the circuits generated by the compiler, all if-else statements are implemented as two (or more) same-latency paths with a multiplexer at the end; it is not possible to pipeline variable-latency operations. The only way to achieve what you want is to write your code in some way that the compiler would not pipeline the part of the code that encompasses the if-else statement; putting whole loops or different function calls on the two sides of the statement can sometimes achieve this.
@HRZ Thanks for the answer
@HRZ написал (-а):
The only way to achieve what you want is to write your code in some way that the compiler would not pipeline
I wonder if this is possible by any means? Can you suggest some example?
Is there any documentation on what code constructs always get pipelined, and which ones don`t?
In my tests, I`ve never seen variable latency in the reports, unless MM interfaces get involved...
Thank you for posting in Intel community forum and hope all is well.
For the concept pipeline for hardware design, you can refer to the best practice guide, it has some explaining there.
Another useful section that helps explain on conditional statement can be found in the page #25 in the link above.
Hope that clarify your doubts.