AVX10/256: xrstor behavior with non-zero upper 256 bits of what would be ZMM regs

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AVX10/256: xrstor behavior with non-zero upper 256 bits of what would be ZMM regs

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Especially with XSAVE component ZMM_Hi256 apparently remaining required to be enabled despite there not being upper halves of the low 16 vector registers, in the AVX10 doc can it please be clarified what XRSTOR behavior is going to be when encountering non-zero upper half values (and non-init state for ZMM_Hi256) in input data, when MAXVL=256?

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