Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.
1111 Discussions

Cache Line Question

CLi37
Beginner
‎01-29-2013 08:58 PM
698 Views

Ivy Bridge has a cache line with length 64 bytes. Suppose I have 4 array on 4 different memory addresses, when I load the first 128bit in each array to 4 SSE registers respectively, then I have loaded 4 cache lines? How many cache lines available?    

0 Kudos

Link Copied

1 Reply
SergeyKostrov
Valued Contributor II
‎01-29-2013 09:16 PM
698 Views
>>... >>How many cache lines available? For example, for Intel(R) Core(TM) i7-3840QM: L1: 256KB -> ( 32KB per core for data & 32KB per core for instructions ) x 4 cores L2: 1024KB -> ( shared for data & instructions 256KB per core ) x 4 cores L3: 8192KB ( 8MB ) -> ( shared for data & instructions & between all cores / 8 logical ) Sizes of these cache lines are different and it depends on a CPU. Please take a look at datasheets at: http://ark.intel.com.
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.