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Hi all
Some preliminar information. I have the latest intel suite (2013) on a Linux machine. In the code, PADDING is a macro expanded to either 16 or 32 depending on the actual vector instruction set used to compile the program (SSE4.2 or AVX).
I am struggling to get aligned accesses on this code:
void f ( double A[restrict 3][4], double x[3][2] ) {
double det = ... ;
double W3[3] __attribute__((aligned(PADDING))) = {0.166666666666667, 0.1666
66666666667, 0.166666666666667};
double FE0[3][4] __attribute__((aligned(PADDING))) = \
{{0.666666666666667, 0.166666666666667, 0.166666666666667},
{... }};for ( int ip = 0; ip <3; ip++)
{
double tmp = W3[ip]*det;
for ( int j = 0; j < 3; j++ )
{
#pragma vector aligned
for ( int k = 0; k < 4; k++ )
{
A+= FE0[ip] *FE0[ip] *tmp;
}
}
}
}
In the caller, A is a static array (of size [3][4]) labelled with __attribute__((aligned(PADDING)))
Despite extensive use of __attribute__ (aligned) and pragmas, by looking at the assembly (generated by icc -O3 -ansi-alias nomefile.c -xSSE4.2 -restrict), it is clear how for the innermost loop unaligned loads and stores (movupd) are used, Shouldn't I expect movapd?
Notice how FE0 and A have been padded from 3 to 4 doubles (and the trip count of loop k extended to 4) so that it is possible to exploit avx aligned instructions.
Thanks for considering my request
Fabio
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