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leec
Beginner
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Intel SIMD - Processor Roadmap

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Does a roadmap exist showing the release of Intel SIMD instructions (SSE, AVX) relative to processor family and date of release? The question I am trying to answer is "If I release software using an Intel SIMD vector instructions at future date X, what SIMD instruction set should I target to insure the maximum installed base?" I'd like to maximize the installed base available for my software, and want to align my roadmap with Intel's so I can have support for future releases available when they hit the street. Thanks!
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knujohn4
New Contributor I
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Does a roadmap exist showing the release of Intel SIMD instructions (SSE, AVX) relative to processor family and date of release? The question I am trying to answer is "If I release software using an Intel SIMD vector instructions at future date X, what SIMD instruction set should I target to insure the maximum installed base?" I'd like to maximize the installed base available for my software, and want to align my roadmap with Intel's so I can have support for future releases available when they hit the street. Thanks!

I do not know about a specific roadmap, but you can find when the processors was introduced here: http://www.intel.com/pressroom/kits/quickrefyr.htm or for newer CPUs, http://ark.intel.com/

MMX was introduced in some steppings of Pentium (Not avaiable on Penitum Pro)
SSE was introduced in Pentium III (Katmai)
SSE2 was introduced in Pentium 4 (Wilamette)
SSE3 was introduced in Pentium 4 (Prescott)
SSSE3 was introduced in Core 2
SSE4_1 was introduced in Penryn
SSE4_2 was introduced in Nehalem
AVX will be avaiable on future CPus (possibly Sandy Bridge?)

Other None SIMD instructions has been added for some of these CPUs

The CPUID instruction will give information about which instructions are available for a given CPU:

http://www.intel.com/Assets/PDF/appnote/241618.pdf

Knut J.



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knujohn4
New Contributor I
123 Views
Does a roadmap exist showing the release of Intel SIMD instructions (SSE, AVX) relative to processor family and date of release? The question I am trying to answer is "If I release software using an Intel SIMD vector instructions at future date X, what SIMD instruction set should I target to insure the maximum installed base?" I'd like to maximize the installed base available for my software, and want to align my roadmap with Intel's so I can have support for future releases available when they hit the street. Thanks!

I do not know about a specific roadmap, but you can find when the processors was introduced here: http://www.intel.com/pressroom/kits/quickrefyr.htm or for newer CPUs, http://ark.intel.com/

MMX was introduced in some steppings of Pentium (Not avaiable on Penitum Pro)
SSE was introduced in Pentium III (Katmai)
SSE2 was introduced in Pentium 4 (Wilamette)
SSE3 was introduced in Pentium 4 (Prescott)
SSSE3 was introduced in Core 2
SSE4_1 was introduced in Penryn
SSE4_2 was introduced in Nehalem
AVX will be avaiable on future CPus (possibly Sandy Bridge?)

Other None SIMD instructions has been added for some of these CPUs

The CPUID instruction will give information about which instructions are available for a given CPU:

http://www.intel.com/Assets/PDF/appnote/241618.pdf

Knut J.



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TimP
Black Belt
122 Views
In case it's not evident, each addition to the instruction set retains upward compatibility. SSE2 and SSE3 code continue to work well on Nehalem and recent AMD CPUs. The most common SSSE3 optimizations aren't desirable on Nehalem, but don't break the code.
In optimizing code for the latest CPUs, issues other than choice of instruction set have been of more importance, such as taking advantage of better performance of unaligned loads (gcc -march=barcelona).
AVX instructions ought to give significant improvements in performance of vectorized code. As there is yet no hardware implementation, the extent of this remains in doubt, and compilers don't have all the optimizations which would be wanted before developing software for release.
To add to the table above, the best known of the Penryn CPUs was Harpertown; the Woodcrest was the first widely produced CPU in Core 2 family, before it was given that name. To continue the confusion, Intel marketing requires Nehalem CPUs to be referred to as Core i7 or Xeon 5500 series, with severe restrictions on use of the name "Nehalem." So, you might think there are more varieties.
The Pentium M and later Core (not Core 2) 32-bit laptop CPUs might be viewed as transitional phases between early P4 and Core 2. They also run standard SSE2 code, although it is not necessarily optimum.
leec
Beginner
122 Views
Quoting - tim18
In case it's not evident, each addition to the instruction set retains upward compatibility. SSE2 and SSE3 code continue to work well on Nehalem and recent AMD CPUs. The most common SSSE3 optimizations aren't desirable on Nehalem, but don't break the code.
In optimizing code for the latest CPUs, issues other than choice of instruction set have been of more importance, such as taking advantage of better performance of unaligned loads (gcc -march=barcelona).
AVX instructions ought to give significant improvements in performance of vectorized code. As there is yet no hardware implementation, the extent of this remains in doubt, and compilers don't have all the optimizations which would be wanted before developing software for release.
To add to the table above, the best known of the Penryn CPUs was Harpertown; the Woodcrest was the first widely produced CPU in Core 2 family, before it was given that name. To continue the confusion, Intel marketing requires Nehalem CPUs to be referred to as Core i7 or Xeon 5500 series, with severe restrictions on use of the name "Nehalem." So, you might think there are more varieties.
The Pentium M and later Core (not Core 2) 32-bit laptop CPUs might be viewed as transitional phases between early P4 and Core 2. They also run standard SSE2 code, although it is not necessarily optimum.

Thank you. These are not exactly the answers I was looking for, but they point me in the right direction and I can dig in and get the answers I think I'm looking for.
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