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Hi all,
This is my first post and I don't know if this is the right newsgroup for the question I have. I am a newbie and reading Intel Software Development manual for my own knowledge purposes. I am confused with Local APIC and it's base memory address in multi-processorenvironment.
Each logical/physical CPU has it's own LAPIC, and documentation states that base address for LAPIC are not shareable amongst multiple processors/CPU's. The base address for LAPIC is 0xFFF00000h as per documentation. That's true for BSP. I am confused how to locate LAPIC base address for other (AP) CPU's?
Your help will be appreciated.
Regards
Gupta
This is my first post and I don't know if this is the right newsgroup for the question I have. I am a newbie and reading Intel Software Development manual for my own knowledge purposes. I am confused with Local APIC and it's base memory address in multi-processorenvironment.
Each logical/physical CPU has it's own LAPIC, and documentation states that base address for LAPIC are not shareable amongst multiple processors/CPU's. The base address for LAPIC is 0xFFF00000h as per documentation. That's true for BSP. I am confused how to locate LAPIC base address for other (AP) CPU's?
Your help will be appreciated.
Regards
Gupta
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Hi
I see section 10.4.1 has the following
I see section 10.4.1 has the following
In MP system configurations, the APIC registers for Intel 64 or IA-32 processors on the system bus are initially mapped to the same 4-KByte region of the physical address space. Software has the option of changing initial mapping to a different 4-KByte region for all the local APICs or of mapping the APIC registers for each local APIC to its own 4-KByte region.
Perhap you saw something different? Can you point to the relevant section?
Thx
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Continuing what Shih Kuo wrote, vol 3 also says the following:
The Pentium 4, Intel Xeon, and P6 family processors permit the starting address of
the APIC registers to be relocated from FEE00000H to another physical address by
modifying the value in the 24-bit base address field of the IA32_APIC_BASE MSR.
This extension of the APIC architecture is provided to help resolve conflicts with
memory maps of existing systems and to allow individual processors in an MP system
to map their APIC registers to different locations in physical memory.
[ This is MSR 01Bh. ]
Are you sure you want to change the base address for the Local APIC of your APs?
The Local APIC address space is private to each processor, so (as far as I know)
one processor can not modify the Local APIC registers of another processor.
Typicaly a BIOS would start up each AP, one at a time, with a SIPI to configure the
SMM base address. The Local APIC address could be modified at the same time.
The Pentium 4, Intel Xeon, and P6 family processors permit the starting address of
the APIC registers to be relocated from FEE00000H to another physical address by
modifying the value in the 24-bit base address field of the IA32_APIC_BASE MSR.
This extension of the APIC architecture is provided to help resolve conflicts with
memory maps of existing systems and to allow individual processors in an MP system
to map their APIC registers to different locations in physical memory.
[ This is MSR 01Bh. ]
Are you sure you want to change the base address for the Local APIC of your APs?
The Local APIC address space is private to each processor, so (as far as I know)
one processor can not modify the Local APIC registers of another processor.
Typicaly a BIOS would start up each AP, one at a time, with a SIPI to configure the
SMM base address. The Local APIC address could be modified at the same time.

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