Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
1135 Discussions

Message Address Register: Redirection hint & Destination mode

Yunju_K_
Beginner
‎01-18-2016 02:58 AM
1,184 Views

Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 3 (3A, 3B, 3C & 3D): System Programming Guide
---

I have a question about the combination of RH bit and DM bit of 10.11.1 Message Address Register Format.

I use the combination as below, it looks like work is going well.
RH = 0
DM = 1

But, there are following mentions in 10.11.1, so the combination of RH = 0 and DM = 1 looks like the wrong combination.

>If RH is 0, then the DM bit is ignored and the message is sent ahead
>independent of whether the physical orlogical destination mode is used.

If wrong, which combination should I use?

My system is AMP（Asymmetric Multiprocessing）system, and it needs to send the MSI interrupt to the plural processors without the lowest interrupt priority.

0 Kudos

Link Copied

1 Reply
Yunju_K_
Beginner
‎01-20-2016 04:14 PM
1,184 Views

Does anybody know about this?

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.