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Hi all.
I have a question about Pentium M cache (but the problem is more general).
By cpuid instruction I observe that it is a set associative cache.
Is there a way to know what block of cache will be used for each memory
address?
In PowerPc processor there is a manner to disable single way of cache so if
I leave only one way active for each set I'm sure of data location.
Is there a similar mechanism for Pentium?
Thanks a lot.
I have a question about Pentium M cache (but the problem is more general).
By cpuid instruction I observe that it is a set associative cache.
Is there a way to know what block of cache will be used for each memory
address?
In PowerPc processor there is a manner to disable single way of cache so if
I leave only one way active for each set I'm sure of data location.
Is there a similar mechanism for Pentium?
Thanks a lot.
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