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Problems with using ippiDilateBorder_1u_C1R

XDu
Beginner
986 Views

Hi,

I am a college student and took the course of basic image processing. So I tested some morphological functions of the ipp library.such as the question I submitted last time about ippiMorphOpenBorder and got a satisfactory reply, I am very grateful.

When I was testing ippiDilateBorder_1u_C1R this time, I noticed that it had two extra parameters: bitOffset. According to the description of the document, I understand it as the offset of src and dst.My tests are as follows:

IppiSize roiSize = { 16, 3 };
Ipp8u pSrc[80] = {
10, 126, 83, 244, 162, 22, 183, 137, 224, 163, 114, 112, 42, 13, 160, 225,
39, 106, 206, 197, 105, 21, 189, 110, 79, 0, 99, 134, 41, 75, 51, 69,
158, 21, 158, 231, 75, 146, 218, 94, 173, 93, 226, 68, 65, 16, 190, 19,
233, 19, 4, 152, 146, 177, 159, 165, 20, 113, 207, 7, 89, 163, 113, 183,
194, 57, 129, 85, 198, 216, 221, 209, 221, 47, 75, 108, 156, 136, 190, 223
};
Ipp8u dst[80] = { 0 };
Ipp8u mask[3 * 3] = { 1,1, 1, 1,1, 1, 1, 1,1 };
IppiSize maskSize = { 3, 3 };
IppiMorphState *spec;
Ipp8u *buffer;
Ipp32s bufferSize, specSize;
ippiMorphologyBorderGetSize_1u_C1R(roiSize, maskSize, &specSize, &bufferSize);
spec = (IppiMorphState*)ippsMalloc_8u(specSize);
buffer = (Ipp8u*)ippsMalloc_8u(bufferSize);
ippiMorphologyBorderInit_1u_C1R(roiSize, mask, maskSize, spec, buffer);

IppStatus sts = ippiDilateBorder_1u_C1R(pSrc, 16, 0,dst, 16,0, roiSize, (IppiBorderType)1, 0, spec, buffer);

for (int i = 0; i < 5; i++){
for (int j = 0; j < 16; j++){
printf("%d ", dst[i * 16 + j]);
}
printf("\n");
}
printf("\n");
printf("\n");
printf("%d\n\n\n\n\n", sts);
ippsFree(buffer);
ippsFree(spec);
system("pause");

When the dstBitOffset is 0, the result is as follows:

127 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0
255 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0
255 255 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

and when the dstBitOffset is 7, the result is as follows:

128 191 127 0 0 0 0 0 0 0 0 0 0 0 0 0
128 255 127 0 0 0 0 0 0 0 0 0 0 0 0 0
128 255 127 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

It's same as when the dstBitOffset is 0,7bits is offset only when storing.

But when the dstBitOffset is 8, the result is as follows:

0 127 255 0 0 0 0 0 0 0 0 0 0 0 0 0
0 254 255 0 0 0 0 0 0 0 0 0 0 0 0 0
0 255 255 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Instead of offsetting a byte in storage as I thought, the result has changed. I don't understand this phenomenon, so I'd like to ask what this BitOffset parameter stands for.
Looking forward to your reply,
Thanks

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5 Replies
VidyalathaB_Intel
Moderator
964 Views

Hi,

Thanks for reaching out to us.

The issue raised by you is reproducible.

We are looking into it. We will get back to you soon.

Regards,

Vidya.

 

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Andrey_B_Intel
Employee
923 Views

Hi,  XDu.

I confirm this issue. dstBitOffset equal 8 means 1 byte of destination offset. As workaround you can add next "if" before calling "ippiDilateBorder_1u_C1R":

if (dstBitOffset >= {
  dst = dst + (dstBitOffset >> 3);
  dstBitOffset &= 7;
}

We will fix this issue in one of the next IPP releases.

Andrey

 

 

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XDu
Beginner
897 Views

thanks for your reply,but I don't quite understand the meaning of the following code.

if (dstBitOffset >= {
  dst = dst + (dstBitOffset >> 3);
  dstBitOffset &= 7;
}

Do you mean to offset dst dstBitOffset/8 bytes ahead of time when dstBitOffset > = 8?

But isn't the role of dsiBitOffset to offset every line of dst from the same bit?And whether there is a same question with srcBitOffset?

Thanks again for the reply,and because I don't know much about the written politeness of English, please forgive me if there is any offense.

XDu

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Gennady_F_Intel
Moderator
670 Views

XDu,

please check the latest IPP 2021 u5 and let us know if the problem you reported still exists.

thanks,

Gennady


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Gennady_F_Intel
Moderator
642 Views

This issue has been resolved and we will no longer respond to this thread. If you require additional assistance from Intel, please start a new thread. Any further interaction in this thread will be considered community only. 



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