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ggalperin
Beginner
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Atomicity of load operation on ia64

Is it guaranteed on ia64 architecture in multi-processor environment that a plain load operation would fetch a 64-bit value atomically? In other words, is it possible that if CPU1 stores some value to a 64-bit memory location and CPU2 fetches the value from the same memory location at the same time, the fetched value would be neither one before nor after store operation?
Thx, ---Greg
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TimP
Black Belt
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64-bit int load on 64-bit architectures is definitely an atomic operation, unlike 32-bit x86, where it is done by a pair of 32-bit loads.
Dmitry_Vyukov
Valued Contributor I
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Quoting - ggalperin
Is it guaranteed on ia64 architecture in multi-processor environment that a plain load operation would fetch a 64-bit value atomically? In other words, is it possible that if CPU1 stores some value to a 64-bit memory location and CPU2 fetches the value from the same memory location at the same time, the fetched value would be neither one before nor after store operation?
Thx, ---Greg

8-, 16-, 32-, 64-, 128-bit aligned loads and stores are indeed atomic on IA-64.
However to get them you probably have to use something like SSE intrinsics or assembly.

For details see:
Intel Itanium Architecture Software Developer's Manual - Volume 2: System Architecture, Revision 2.2
http://www.intel.com/design/itanium/manuals/245318.htm
(4.5 Memory Datum Alignment and Atomicity)

Dmitry_Vyukov
Valued Contributor I
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Quoting - Dmitriy Vyukov

8-, 16-, 32-, 64-, 128-bit aligned loads and stores are indeed atomic on IA-64.
However to get them you probably have to use something like SSE intrinsics or assembly.

For details see:
Intel Itanium Architecture Software Developer's Manual - Volume 2: System Architecture, Revision 2.2
http://www.intel.com/design/itanium/manuals/245318.htm
(4.5 Memory Datum Alignment and Atomicity)


Hmmm... Do you sure that you mean exactly IA-64 (i.e. Itanium)? Probably you mean Intel 64 (i.e. x86-64)...
However, 8-, 16-, 32-, 64-, 128-bit aligned loads and stores are also atomic on IA-32 (i.e. x86) and on Intel 64 (i.e. x86-64). But don't try to extend this to the C language, for example. In order to get 128-bit atomic load/store you have to emit some particular machine instruction, not just plain access to 128-bit variable in the C source.

ggalperin
Beginner
130 Views

Quoting - Dmitriy Vyukov

Hmmm... Do you sure that you mean exactly IA-64 (i.e. Itanium)? Probably you mean Intel 64 (i.e. x86-64)...
However, 8-, 16-, 32-, 64-, 128-bit aligned loads and stores are also atomic on IA-32 (i.e. x86) and on Intel 64 (i.e. x86-64). But don't try to extend this to the C language, for example. In order to get 128-bit atomic load/store you have to emit some particular machine instruction, not just plain access to 128-bit variable in the C source.

Yes, I meant ia64 (Itanium). Thanks for the details. Will definitely use asm instructions and align data properly.
Just want to clarify: even if a 64-bit word is only 8-bit aligned, I can still emit a certain atomic load/store instruction on Itanium that will be atomic? Thx.
TimP
Black Belt
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Quoting - ggalperin
even if a 64-bit word is only 8-bit aligned, I can still emit a certain atomic load/store instruction on Itanium that will be atomic?
On IA64. 64-bit memory access has to be 64-bit aligned in order to be performed by a single instruction. Unaligned access will abort the application, unless it is done by several smaller width instructions. It makes no difference whether asm is used for the load alone, compilers don't provide for unaligned loads. If you have a BIOS option set to retry unaligned memory access, that is very slow, and not atomic.
For load-update-store, you have several options, including OpenMP atomic.
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