- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Let's say I have a pointer char *p. How can I implement behavior, in which depending on which processor is doing pointer dereference, different data is accessed?
I want something like Thread Local Storage, but for HW thread (something like HW-thread Local Storage, CPU Local Storage).
char *p = ...; // Initialization should be done in some special way, probably
char *local_p = get_hwls(p);
I want something like Thread Local Storage, but for HW thread (something like HW-thread Local Storage, CPU Local Storage).
char *p = ...; // Initialization should be done in some special way, probably
char *local_p = get_hwls(p);
Link Copied
3 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Maybe one of us is missing a point. As tls would be associated with a software thread, hardware affinity would associate both the thread and the tls sufficiently closely with hardware cache and local RAM to give the performance benefits.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Quoting - tim18
Maybe one of us is missing a point. As tls would be associated with a software thread, hardware affinity would associate both the thread and the tls sufficiently closely with hardware cache and local RAM to give the performance benefits.
Indeed. Also, if the software thread is not tied to a particular hardware thread then the code would be pretty meaningless: the hardware thread used to set or retrieve the value could in principle be distinct to that used to run the code immediately before and after the value was accessed.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The only HW local storage you have is/are the registers (IA). And depending on your scoping interpretation, this might extend into L1, L2, L3 cache.
When using O/S calls for restricting the affinity of a software thread to a HW thread you can have some measure of selection for the cache storage
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page