I am trying to understand how Machine Check Architecture (MCA) works. It consists of a set of global configuration/status MSRs and several bank of MSRs for error logging.
In Intel Manual Vol.3 Ch.35, I see some MCA global MSRs are "thread-scoped", such as:
IA32_MCG_STATUS (0x17AH) in Xeon Phi processor.
The manual says in Vol.3. Ch.35.6:
“Thread” means this bit field must be programmed on each logical processor independently.
So, if I want to manipulate some bits of a thread-scoped MSR, I have to make sure that the code containing the manipulation logic is executed on the logical processor which owns that thread-scoped MSR.
And although the thread-scoped MSR has only one fixed address (e.g. 0x17AH for IA32_MCG_STATUS), visit this same address on different logical processor will visit different MSRs.
Is my understanding right?
If so, how can I designate which logical processor to run my code? For example, I want to write to a thread-scoped MCA MSR so that I can inject/spoof some hardware error to validate the whole error handling stack.
- Parallel Computing
The details will depend on your OS and whether you are running in the kernel or in user space....
If you are running on a Linux system, running in user space, you can use the /dev/cpu/
If you are on a Linux system and running in kernel space (e.g., inside a device driver), there are helper routines defined to execute the RDMSR instruction on a target logical processor. In the 3.10 kernels that I use the interfaces are "rdmsr_safe_on_cpu()" and "wrmsr_safe_on_cpu()". These interfaces set up the inter-processor interrupts necessary to start up a kernel process on the target core and have it read the MSR on that core, then return the value to the calling process.