How to separately control MSRs on Intel Core 2

[zhangyihere]

Hi all,

In the Software Developer's Manual, it is said that, for Intel Core 2 processor family, MSRs are categorized into Unique and Shared, and Unique means each processor core has a separate MSR.

So, I would like to ask if I could separatelycontrol the Unique MSRsby each core? Such asenabling L1cache prefetcher on one core and disabling the L1 cache prefetcher on the other core? Andhow should I do?

Thanks in advence!

[TimP]

In my experience, we had control only over (strided) hardware prefetch, and adjacent sector (cache line pairing) prefetch, all cores set the same.

[zhangyihere]

Thanks for the fast reply! But in some literature, I have read that all cache prefetchers ontheir platform are percore
configurable except the L2 adjacent line prefetcher. The platform they use is Intel Xeon 5160.

Could you give me some furtheradvice on how toimplement suchfunctions?

Thanks

[TimP]

http://stackoverflow.com/questions/784041/how-do-i-programatically-disable-hardware-prefetching
gives you advice on where to look in linux kernel and /dev/ for hardware prefetch settings.
http://software.intel.com/en-us/articles/optimizing-application-performance-on-intel-coret-microarchitecture-using-hardware-implemented-prefetchers/ shows a setup screen for a BIOS which includes these settings (seen on only a few servers)
Tinkering with these settings seems to be much less popular than it was several years ago, judging by the reduced number of Google hits.
When you say Core 2, I don't think you mean the Xeon 7xxx 4-socket servers with L3 cache, a special case where disabling hardware prefetch might have produced performance gains, perhaps 5%, on certain job types, and, of course, much large losses on others.
The adjacent sector (cache line pairing) might more often reduce performance, particularly where threads operate about 1 cache line apart, with one reading and the other writing data. Perhaps people have learned to improve their threading rather than trying to patch up these situations by disabling prefetch.

[mahmoudgalal1985]

Quoting - tim18

http://stackoverflow.com/questions/784041/how-do-i-programatically-disable-hardware-prefetching
gives you advice on where to look in linux kernel and /dev/ for hardware prefetch settings.
http://software.intel.com/en-us/articles/optimizing-application-performance-on-intel-coret-microarchitecture-using-hardware-implemented-prefetchers/ shows a setup screen for a BIOS which includes these settings (seen on only a few servers)
Tinkering with these settings seems to be much less popular than it was several years ago, judging by the reduced number of Google hits.
When you say Core 2, I don't think you mean the Xeon 7xxx 4-socket servers with L3 cache, a special case where disabling hardware prefetch might have produced performance gains, perhaps 5%, on certain job types, and, of course, much large losses on others.
The adjacent sector (cache line pairing) might more often reduce performance, particularly where threads operate about 1 cache line apart, with one reading and the other writing data. Perhaps people have learned to improve their threading rather than trying to patch up these situations by disabling prefetch.

Thanks for the links