Is there any emulator(PMEP) for persistent memory?

[John_A_]

I've been studying the performance of persistent memory in Linux.

And I'm using the DRAM with Dax instead of Persistent memory.

However, in some paper(A study of Application Performance with Non-Volatile Main Memory, System Software for Persistent Memory[EuroSys 14])

I saw there is some emulator for persistent memory(PMEP).

I googled intensively about that, but I couldn't found the information of the PMEP.

So is there any emulator for persistent memory?

[gaston-hillar]

Hi John,

Somebody else asked a similar question in this thread: https://communities.intel.com/thread/105736

He was recommended addressing his question through the SSD department.

So, probably they can also help you.

[bill__grace]

Hello John,

I have heard about Quartz, an emulator for persistent memory. However, you may cross-check it again from the below article.

Thanks,

Grace

[jimdempseyatthecove]

Back in the 1960's the systems I programmed on had persistent memory in the form of core memory. In the event of a power outage, a power fail interrupt would occur (assuming your system had PF option), the interrupt service would save the register states (small number), and say within 16us when all was saved, issue a Halt instruction. Upon power restoration, either you manually entered the restart location (e.g. 0000), and pressed Run, or the hardware option did this for you.

Barring the fact that you cannot get or afford core memory, and that there is no suitable replacement for 10's -  100's GB of NVM....
Systems (non-embedded) today have significantly large register sets to save as well as multiple pending cache flushes to perform. Picking numbers out of the air 28-core 56-thread with AVX512:

(32 AVX512 registers)*56 + (32 GP registers)*56 + (pending writes, which may be RMW)*(28 or 56)

The NVM may not necessarily have a data bus width of 512-bits. If it does (32*56) + (32/8)*56 + ??4*28

A minimum of 140 writes to NVM or 2x, 4x, 8x, 16x this depending on the memory data bus.

True persistent memory systems for desktop/notebook/cellphone/server will have to wait until NVM completely replaces main memory as well as register and cache (assuming cache would still be required). The transitioning to this will wait until NVM both bulk and within CPU is as cost effective as the current dynamic memory/register.

What has been bantered about, amounts to a check-pointing system that periodically checkpoints either all or some subset of the system such that all or some subset of the system can be wound back to a prior saved state. Note, checkpoint is not the same as persistent memory.

Jim Dempsey

[jimdempseyatthecove]

I just had a thought that if one were to choose an Intel CPU that has TSX (transactional) capability, .AND. NVM main memory, that potentially the O/S and application code could be completely rewritten such that it starts and terminates transactions, in otherwise non-transactional sections of code, with only a minimal set of registers that require save state (PC and stack pointer). The TSX transaction commit would have to accomidate a power fail during commit (IOW not update PC until after commit completes). In this manner, you could greatly reduce the time to save state.

Jim Dempsey