Memory Conisstency Model for Intel64 / Xeons 55XX, 56XX)
I am trying to find a concise specification or at least a concrete description of the memory model supported by the Intel64 ISA on the Xeons 55XX/56XX/70XX processors.
The only discussion I could come accorss is an oldish white paper: "Intel 64 Architecture Memory Ordering White Paper", Revision: 1.0, SKU: 318147-001, Date: August 2007.
I am really interested in a more complete desription of the memory model followed at the EP and EX platforms. From the white paper above there is a total store ordering across different processors. It is not very clear though how events such as, data prefetching or cache line interventions are handled.