MicroArchitectural Information on IntelCore2Duo E6400

[prads]

Hello,
I wanted some information regarding the microarchitecural specifications of Intel Core 2 Duo E6000 series (specifically E6400) Desktop Computer. I looked for them in a lot of Intel's docs but couldnot find them. Here are the questions. What is its?
1. Issue width
2.Decode width
3.Load/Store queue
4.Memory Access Latency
5.Memory Access Bus width
6.Instruction TLB
7.Data TLB
8.Total No. of Integer/Multiplier/Divider
9.Memory System ports
10.No. of Floating Point ALU
11.F.P. Mul/Div
12.Instrn/Data TLB miss latency
Thanks,
prads

[TimP]

Many of these items are the same as other Core architecture variants, such as Woodcrest. I know of only the one set of docs covering all of them.
For TLB miss latency, there are several cases, which I doubt have been documented fully on any of these CPUs. Note the 2 levels of TLB and the 2 different designations of cache levels (0/1 and 1/2).
In case you didn't see it, you might find this interesting:
http://software.intel.com/file/944
I note that it doesn't necessarily agree with other docs; for example, it says the small DTLB has 8 entries, where I've seen 16 written elsewhere. Nor can I explain why it talks about L0, L1, and L2.