Hi,
Thanks for your reply - nice to know I wasn't the only one confused... :)
Unfortunately I don't have a "6-core with HT" CPU here for testing. To be honest, I didn't realize they'd been released yet - 6-core "Dunnington" without HT released, and 6-core "Gulftown" with HT expected in the first half of next year?
I assume that all Nehalem based CPUs do/will report a total of 16 APIC IDs reserved (with <= 16 used) and 8 APIC IDs reserved for the first logical CPU in each core (with <= 8 used); and that a Nehalem with hyper-threading disabled in the BIOS or disabled in the silicon reports the same as a Nehalem that's using hyper-threading.
I'm mostly upating old code that gathers all information about each CPU from various sources (CPUID, and table look-ups on older CPUs where information is missing from CPUID or CPUID isn't supported) and puts the information into a clean/consistant structure, so that later software doesn't need to deal with the horrendous mess that CPUID has become.
Note: To understand what I mean by "horrendous", try writing code that detects cache sizes and types (including how many other CPUs share the cache), that works for a wide variety of CPUs from a wide variety of CPU manufacturers, and takes into account all known CPU errata.Cheers,
Brendan