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Altera_Forum
Honored Contributor I
1,460 Views

10500 syntax Error

Hey, I'm a beginner and new to VHDL coding. 

i was assigned to write code for Simple Moving average Filter with 16 bit ADC by college professor. 

since i'm unable to figure out how to interface adc i have written code just for moving average. 

 

 

LIBRARY IEEE; 

USE IEEE.std_logic_1164.all; 

USE IEEE.std_logic_arith.all; 

 

 

Entity movavg is  

 

 

Port(in_ma : IN std_logic_vector(15 DOWNTO 0); 

out_ma : OUT std_logic_vector(15 DOWNTO 0););  

 

end movavg; 

 

 

ARCHITECTURE Behavourial OF movavg IS 

signal in_ma : std_logic_vector(15 DOWNTO 0); 

signal out_ma : std_logic_vector(15 DOWNTO 0); 

 

 

inp <= unsigned(in_ma); 

x <= to_integer(inp); 

 

 

for i in 0 to 4195 loop 

y(i) <= y(i)+x(i+1); 

y_sum <= y/4196 ; 

 

 

end loop; 

 

 

y_out <= to_unsigned(y_sum,16); 

out_ma <= std_logic_vector(y_out); 

 

 

end Behavourial;  

 

 

i'm getting following error  

Error (10500): VHDL syntax error at movavg.vhd(13) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable" 

Error (10500): VHDL syntax error at movavg.vhd(21) near text "<="; expecting ":", or "," 

 

can someone help me with this ? 

also if there are any additional errors please let me know  

Thank you.
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7 Replies
Altera_Forum
Honored Contributor I
73 Views

well plenty of errors. The immediate syntax error is that you need to insert [begin] after signal declaration. 

Bu your design doesn't make sense, you are asking for thousands of adders.
Altera_Forum
Honored Contributor I
73 Views

You have repeated io as internal signals. 

You have used x/y with no declaration 

averaging needs one or two adder/subtractor only but many delay stages
Altera_Forum
Honored Contributor I
73 Views

 

--- Quote Start ---  

well plenty of errors. The immediate syntax error is that you need to insert [begin] after signal declaration. 

Bu your design doesn't make sense, you are asking for thousands of adders. 

--- Quote End ---  

 

 

thank you for reply. 

actually the professor in-charge asked me to write code for moving average for 4196 points and find out problems that may occur. 

This is just for practice purpose to get me used to VHDL.
Altera_Forum
Honored Contributor I
73 Views

You better not show it to the professor until you have good practical design. Apologies but with +4000 adders he might get heart attack if eldely like me.

Altera_Forum
Honored Contributor I
73 Views

 

--- Quote Start ---  

You better not show it to the professor until you have good practical design. Apologies but with +4000 adders he might get heart attack if eldely like me. 

--- Quote End ---  

 

 

thank you sir :lol: 

Will make sure this code does not reach to him. 

In my defense, I wrote this code with just 2 days of reading VHDL book (by Douglas Perry). 

Will definitely try and get better at practical design. 

if possible can you recommend some books with more practical examples/codes just to get familiar with VHDL.
Altera_Forum
Honored Contributor I
73 Views

 

--- Quote Start ---  

thank you sir :lol: 

Will make sure this code does not reach to him. 

In my defense, I wrote this code with just 2 days of reading VHDL book (by Douglas Perry). 

Will definitely try and get better at practical design. 

if possible can you recommend some books with more practical examples/codes just to get familiar with VHDL. 

--- Quote End ---  

 

 

For running average: pass input through 4196 stages (registers but memory based fifo is more realistic). accumulate continuously and subtract last stage from result of accum. 

The accum is just an adder with feedback from its output. djust bitidth to input bitwidth plus accum growth of 2^13
Altera_Forum
Honored Contributor I
73 Views

See this online training for a good start with VHDL: 

 

https://www.altera.com/support/training/course/ohdl1110.html
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