10G Ethernet MAC Design example issue with Modelsim Altera starter edition 10.1e

[Altera_Forum]

Hello, 

I'm using Quartus II 14.0. I wanted to simulate the design example for 10G Ethernet MAC ip core. I'm following Altera Document for step by step procedure for 10G E MAC ip core Mega function user guide. when i run the do tb_run.tcl , the modelsim fails to simulate and it gives an error.  ------------------------------------------------------------------------------------------------------------------------------------------------------------- # Top level modules:# altera_eth_10g_mac_xaui_eth_10g_design_example_0_eth_loopback_composed_mm_interconnect_0_rsp_mux# Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013# -- Compiling module altera_eth_10g_mac_xaui_eth_10g_design_example_0_eth_loopback_composed_mm_interconnect_0_rsp_demux# ** Error: (vlog-7) Failed to open library file "D:/Altera_working/altera_eth_10g_mac_xaui/altera_eth_10g_mac_xaui/simulation/mentor/libraries/rsp_demux/altera_eth_10g_mac_xaui_eth_10g_design_example_0_eth_loopback_composed_mm_interconnect_0_rsp_demux" in read/write/execute mode. # # No such file or directory. (errno = ENOENT) # ** Error: ./..//submodules/altera_eth_10g_mac_xaui_eth_10g_design_example_0_eth_loopback_composed_mm_interconnect_0_rsp_demux.sv(99): Verilog Compiler exiting# ** Error: D:/altera/14.0/modelsim_ase/win32aloem/vlog failed. # Error in macro ./tb_run.tcl line 32# D:/altera/14.0/modelsim_ase/win32aloem/vlog failed.# while executing# "vlog -sv "$QSYS_SIMDIR/submodules/altera_eth_10g_mac_xaui_eth_10g_design_example_0_eth_loopback_composed_mm_interconnect_0_rsp_demux.sv" -w..."# ("eval" body line 5)# invoked from within# "com" --------------------------------------------------------------------------------------------------------------------------------------------------------------  what could be the problem.?? Do i need to set ENV_VARIABLES for modelsim..? Please help me.  thanks & regards Vinod Kumar

[Altera_Forum]

Are you using the same version of Quartus and Modelsim that the design was developed with?

[Altera_Forum]

Hi, 

Yes. I'm using same version as used by Reference design document. There are two design examples in Ethernet directory. If i run simulation for "altera_eth_10g_mac_base_r" design example, simulation will work fine. If i run another design example "altera_eth_10g_mac_xaui", simulation will through error as mentioned in previous thread. what could be the reason.? Please help me to resolve this issue.?  thanks and regards Vinod Kumar

[Altera_Forum]

Probably some files are missing. Since the other design is working fine, I would suggest you contact Altera on this.

[Altera_Forum]

Hi Vinod, 

 Just curious if you receive any resolution from Altera on this?