Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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2-decade up/down BCD counter ,, need help

Altera_Forum
Honored Contributor II
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Hi all.. 

i need some help in my project, i have attached the PDF file. 

so please if anyone can help.. Thank u ;)
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Altera_Forum
Honored Contributor II
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Yes I can help. Read the assignment, and do what it says. 

 

You are welcome. 

 

If you have any *specific* question or problem though, we can give you a more detailed answer.
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Altera_Forum
Honored Contributor II
295 Views

i need the state diagram please,, thank u ;)

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Altera_Forum
Honored Contributor II
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That's not really what I call a specific question. Show us what you've done so far and what you don't understand. You won't get a ready made solution here.

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Altera_Forum
Honored Contributor II
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Looking beyond your homework laziness for a moment - the quality of this class material is poor. Asking pupils for a state diagram for this counter is fairly pointless, since it's got only the obvious ~100 internal states. On a ten by ten grid it's not so bad to draw out the Up/Down transitions, but the Load input jumps you to any state, from any state (depending on the 8 Load data pins) so that will cover the diagram in possible transitions. No mention of the clock input anywhere. No mention of what stimulus is required for the timing diagrams (how many cycles of the four examples?). Good luck.

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