I'm new to VHDL and digital design and am designing a simple counter which counts from 0 to 15. Currently I am using four toggle flip flops that will toggle when all lower-odder bits are '1'. The board toggles correctly for four number, skips four, then continues. For example, from 15, 0, 1, 2 then to 7, 8, 9, 10. The counter is synchronous and is based off of a modified clock. When T (toggle bit) is 1, Q(output) toggles. Originally, I assign the temp bit to '1', because when assigned to '0' VHDL throws a bunch of latch errors, but I'm not sure why. Help would be greatly appreciated!
clk1 : clk_div2 port map (clk => clk, sclk => t12);
tff1 : TFF port map ( T => temp, Enable => en, Clk => t12, Q => t1);
tff2 : TFF port map ( T => t5, Enable => en, Clk => t12, Q => t2);
tff3 : TFF port map ( T => t6, Enable => en, Clk => t12, Q => t3);
tff4 : TFF port map ( T => t7, Enable => en, Clk => t12, Q => t4);
togg1 : process (t1, t2, t3, t4) begin
t5 <= t1;
t6 <= t2;
t7 <= t3;
if (t1 = '1') then t5 <= '1';
elsif (t2 = '1' AND t1 = '1') then t6 <= '1';
elsif (t3 = '1' AND t2 = '1' AND t1 = '1') then t7 <= '1';
end if;
end process;
data(3 downto 0) <= t4 & t3 & t2 & t1;
t11 (7 downto 4) <= "0000";
t11 (3 downto 0) <= data;
