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Hi, I am new to VHDL and trying to create a VHDL module for a 7 segment decoder. The code I used is belowlibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity segementdecoder is
Port (sevenseg_A : out STD_LOGIC_VECTOR (3 downto 0);
sevenseg_C : out STD_LOGIC_VECTOR (6 downto 0);
digit : in STD_LOGIC_VECTOR (3 downto 0);
Dsel : in STD_LOGIC_VECTOR (1 downto 0));
end segementdecoder;
architecture Behavioral of segementdecoder is
signal D3 : STD_LOGIC_VECTOR (3 downto 0);
signal D2 : STD_LOGIC_VECTOR (3 downto 0);
signal D1 : STD_LOGIC_VECTOR (3 downto 0);
signal D0 : STD_LOGIC_VECTOR (3 downto 0);
begin
process ( digit )
begin
case digit is
when "0000" => sevenseg_C <= "0000001" ; --0
when "0001" => sevenseg_C <= "1001111" ; --1
when "0010" => sevenseg_C <= "0010010" ; --2
when "0011" => sevenseg_C <= "0000110" ; --3
when "0100" => sevenseg_C <= "1001100" ; --4
when "0101" => sevenseg_C <= "0100100" ; --5
when "0110" => sevenseg_C <= "0100000" ; --6
when "0111" => sevenseg_C <= "0001111" ; --7
when "1000" => sevenseg_C <= "0000000" ; --8
when "1001" => sevenseg_C <= "0000100" ; --9
when "1010" => sevenseg_C <= "0001000" ; --A
when "1011" => sevenseg_C <= "1100000" ; --B
when "1100" => sevenseg_C <= "0110001" ; --C
when "1101" => sevenseg_C <= "1000010" ; --D
when "1110" => sevenseg_C <= "0110000" ; --E
when "1111" => sevenseg_C <= "0111000" ; --F
when others => sevenseg_C <= "0111111" ; --
end case;
end process;
process (Dsel, D3, D2, D1, D0)
begin
case Dsel is
when "00" => SevenSeg_A <= "0111"; -- AN 3
digit <= D3;
when "01" => SevenSeg_A <= "1011"; -- AN 2
digit <= D2;
when "10" => SevenSeg_A <= "1101"; -- AN 1
digit <= D1;
when "11" => SevenSeg_A <= "1110"; -- AN 0
Digit <= D0;
when others => null;
end case;
end process;
end Behavioral;
When I check the syntax I get the following errorsERROR:HDLParsers:800 - "C:/Users/Alex/Desktop/VHDL/argser/dasfas.vhd" Line 51. Type of digit is incompatible with type of D3.
ERROR:HDLParsers:800 - "C:/Users/Alex/Desktop/VHDL/argser/dasfas.vhd" Line 54. Type of digit is incompatible with type of D2.
ERROR:HDLParsers:800 - "C:/Users/Alex/Desktop/VHDL/argser/dasfas.vhd" Line 57. Type of digit is incompatible with type of D1.
ERROR:HDLParsers:800 - "C:/Users/Alex/Desktop/VHDL/argser/dasfas.vhd" Line 60. Type of Digit is incompatible with type of D0. I do not understand how type of digit is incompatible with type of D3,D2,D1,D0 as they are both vectors. Can anyone advice me on how to amend the code? Thanks in advance
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"digit" is defined as Input. Therefore the values for "digit" must come from outside. You try to load "digit" with an internal signal (D0, D1, D2, D3).
Where does the values for D0 to D3 come from? I don't see an Input for them.- Mark as New
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I changed digit to an internal signal and D0, D1, D2 and D3 should have been inputs signals, After those changes the code work.
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