Hi,everyone.
I am a new here. when i use a dcfifo in my project, i encounter a confusing problem. wrclk is 200MHz and rdclk is 250MHz, they come from different PLL output. The aclr signal is generated from a low clock(20MHz). Before inputing the DCFIFO, the signal aclr is synchronized by the wrclk using 2 level DFF. I used to do this in my .sdc file:
set_false_path -from clk_20M -to clk_200M# (1)
set_false_path -from clk_200M -to clk_250M# (2)
because the aclr is ealier many clock cycles than the wrreq and data and the number of the transfer path between the clk_20M and clk_200M is only one, I think it is safe to use the sentence (1). the recovery report will fail if don't cut the path between wrclk and rdclk. Can't the synchronized aclr provide the protection about the recovery? Is it safe to cut the path between wrclk and rdclk? I used to simulate the project with Timing model in Modelsim, it worked correctly, but today this method isn't work. the signal that DCFIFO output is metastable. why?
Anyone who can help me? Many thanks for every reply!:confused:
