Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

A bug in quartus_pgm ?

Altera_Forum
Honored Contributor II
1,592 Views

Hi,everyone. 

I follow the example20-1 in the altera's file"qts_qii53022.pdf".The example20-1 in page 31.The command and result are as follows: 

quartus_pgm -c usb-blaster -m jtag -o bpv;test.sof 

Info: ******************************************************************* 

Info: Running Quartus II Programmer 

Info: Version 7.2 Build 151 09/26/2007 SJ Full Version 

Info: Copyright (C) 1991-2007 Altera Corporation. All rights reserved. 

Info: Your use of Altera Corporation's design tools, logic functions  

Info: and other software and tools, and its AMPP partner logic  

Info: functions, and any output files from any of the foregoing  

Info: (including device programming or simulation files), and any  

Info: associated documentation or information are expressly subject  

Info: to the terms and conditions of the Altera Program License  

Info: Subscription Agreement, Altera MegaCore Function License  

Info: Agreement, or other applicable license agreement, including,  

Info: without limitation, that your use is for the sole purpose of  

Info: programming logic devices manufactured by Altera and sold by  

Info: Altera or its authorized distributors. Please refer to the  

Info: applicable agreement for further details. 

Info: Processing started: Fri Nov 13 19:19:22 2009 

Info: Command: quartus_pgm -c usb-blaster -m jtag -o bpv;test.sof 

Info: Using programming cable "USB-Blaster [USB-0]" 

Info: Started Programmer operation at Fri Nov 13 19:19:28 2009 

Info: Ended Programmer operation at Fri Nov 13 19:19:28 2009 

Info: Quartus II Programmer was successful. 0 errors, 0 warnings 

Info: Allocated 162 megabytes of memory during processing 

Info: Processing ended: Fri Nov 13 19:19:28 2009 

Info: Elapsed time: 00:00:06 

 

But the FPGA was not programmed.I don't know why? 

best wishes 

han
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
783 Views

do you mean by not programmed that the fpga lost it's configuration after power off ? thats normal as the altera FPGAs are volatile types. 

the quartus programmer is used to "test" your image and let it run on the target.
0 Kudos
Altera_Forum
Honored Contributor II
783 Views

Thank you for your reply,MSchmitt.But I didn't power off.I think the sof file wasn't downloaded,because the blaster just flash three times,it didn't light for some time.

0 Kudos
Altera_Forum
Honored Contributor II
783 Views

 

--- Quote Start ---  

I follow the example20-1 in the altera's file"qts_qii53022.pdf". 

--- Quote End ---  

Not actually. You modified a command for CPLD device using a *.pof file. Unfortunately, *.sof file download has neither a blankcheck nor a  

verify option. The invalid options may be reason enough for the Quartus Programmer to ignore the complete command. I didn't check. 

 

Do you have particular reasons not to use the interactive programmer tool? It would be at least helpful to find out about valid programming options.
0 Kudos
Altera_Forum
Honored Contributor II
783 Views

Hi FvM. 

Thank you for you advise.I have used the interactive programmer tool and .sof file was download successfully. 

Now I can download successfully by use the command "quartus_pgm -c usb-blaster -m jtag -o p;test.sof@2".The blaster cann't choose the right device with the verify option comand,So I must help the blaster to choose the devie_2 by the command "@2".  

thanks all for your pure-hearted replay.
0 Kudos
Altera_Forum
Honored Contributor II
783 Views

hi, 

is it possible to program the device through the script. 

I want to use quartus_pgm -c USB-Blaster -m JTAG -o P;mux2_1.sof 

in my script show below.Plz correct me where I am wrong. 

 

email::ksharma30.AT. gmail 

 

///////////////////////////////////////// 

load_package flow 

 

project_new test3 -overwrite 

# Assign family, device, and top-level file 

set_global_assignment -name FAMILY CycloneII 

set_global_assignment -name DEVICE EP2C70F896C6 

set_global_assignment -name VERILOG_FILE mux2_1.v 

set_global_assignment -name TOP_LEVEL_ENTITY mux2_1 

# Assign pins 

set_location_assignment -to clk Pin_AD15 

set_location_assignment -to reset Pin_T29 

# compile the project 

execute_flow -compile# execute_module -tool map# execute_module -tool fit# execute_module -tool tan# execute_module -tool asm# execute_module -tool eda 

# Other assignments could follow 

quartus_pgm -c USB-Blaster -m JTAG -o P;mux2_1.sof 

 

project_close 

////////////////////////////////////////// 

 

Thanks
0 Kudos
Reply