ADC combining DDR channels

Altera_Forum · ‎07-10-2012

I have an ADC that is inputting data serially to the FPGA with a frame clock at 50MHz on two channels. On one channel the sample is complete on the rising edge of the frame clock, the other channel on the falling. This data is then combined with a 100MHz clock created from the frame clock through a PLL.

I initially had used the falling edge of the 100MHz clock to do the combining because I was afraid that the edges of the two clocks couldn't be guaranteed and that there would be timing violations. However, after testing it on the rising edge of the 100MHz clock, timequest reports better timings. It doesn't seem to show any issue of the edges not aligning.

Is this relationship between the 50MHz and the 100MHz guaranteed by the PLL?

Altera_Forum · ‎07-10-2012

Hard to say exactly what's going on but..

Ideally, unless the you specify a phase shift, the rising edge of the 100 MHz generated clock will be aligned with edges of the 50 MHz base clock.

And in normal compensation mode, the PLL will make it pretty much so: the rising edge of the 100 MHz clock at the registers will be aligned with the edges of the 50 MHz clock at the input pin, plus/minus a bit of skew.

Does this help?

Altera_Forum · ‎07-10-2012

Ok, that is good enough for me then. I guess I was over thinking the issue and thought that the clock skew could be enough to disrupt the timing of the register.