ADC in VHDL for Cyclone IV E

[Altera_Forum]

Hi guys, 

 I am new to VHDL and cyclone IV, I just received it from my supervisor and am suppose to finish creating a program for ADC by next week. Just to let you all know, I have already read through the user manual on ADC and also the ADC manual for DE0-Nano ADC controller.   Basically I cant seem to grasp whether i still need to assign the pins to the ADC gpios in VHDL or are they simply connected and i do not need to to anything? And how do i read from these pins, I'm basically confused by the ADC pins and would like some help on them.  If anyone can provide a sample VHDL code or a more detailed manua on ADC w/ VHDL on preferably cyclone IV E,it would be great.  Thank you all!

[Altera_Forum]

In your quertus project, you need to ensure the signal names from your VHDL are mapped to pins via the correct Pin assignments to connect to the ADC. The relavent pin numbers should be in the documentation.

[Altera_Forum]

for example, my ADC has 4 pins that supposedly inter connected between the FPGA and the ADC, 

SCLK, CS, DataIN, DataOUT  In VHDL, do I declare them with respect to the FPGA? which would mean SCLK, CS and DataIN would be OUT pins, and DataOUT would be an IN pin?  or is it with respect to the ADC, which would indicate otherwise?

[Altera_Forum]

What does the datasheet for the ADC say? For example it should say whether it requires an SCLK generated elsewhere or if it is generated from the ADC.  

But yes, assuming the naming is respect to the ADC, then you need to delcare the pins as you say. But you could call them banana, apple, orange and pear if you like, aslong as they behave correctly and are connected properly.