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ADC timing constraint problems

Altera_Forum
Honored Contributor II
‎02-14-2011 04:19 PM
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We have some issues with what I believe is the timing constraints that we have on the ADC interface on the FPGA. I was wondering if someone could give me a hand and help me with the input (min,max) delay constraints. The ADC is clocking data out on falling edge and the FPGA will latch the data on rising edge. The data is single data rate. The clock rate is 92.16 MHz and Tco is between 0 – 0.6 ns. The tracks are matched to within 0.2 in.  

 

 

 

thank you 

 

 

/Boris 

 

 

 

 

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Altera_Forum
Honored Contributor II
‎02-15-2011 08:29 AM
529 Views

Have a look at the timequest user guide (http://www.alterawiki.com/wiki/timequest_user_guide) to help you set up your timing requirements.

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