ALTDDIO_IN的 IP核如何支持148.5M高清数据。

[均符]

在使用ALTDDIO_IN的 IP核时遇到的问题 ：

查看该ip核数据手册，发现频率最高只支持到133MHZ，但我们的数据最高时钟频率是148.5Mhz，

这样就会导致频率在148.5Mhz时，该ip核解码出来的数据不对，如果要用该IP核，应该如何解决这个问题。

项目所使用的软件版本是Quartus Prime Standard Edition 17.1

          FPGA芯片是5CGTFD7D5F27C7N

[KhaiChein_Y_Intel]

Hi,

According to the spec, the maximum frequency of 133MHz is allowed. You will probably see a timing violation if you compile with frequency higher than the maximum allowable frequency.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

May I know if you have any updates?

Thanks.

Best regards,

KhaiY

[均符]

We wrote verilog Code to replace the "DDIO_IN" IP. We've got it. Thank you!