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15557 Discussions

ALTPLL simulation model bug

Honored Contributor II

Hello there, 

I haven't double checked if this exists in this forum, but this confused me a week! 

And I found it is a bug, so I should notice Altera to fix it in the future. 


Please check the verilog simulation model for altpll module (it should be in altera_mf.v file, the laptop is not on my hand right now, so please search it, if it is not there) 


When I use the "Cyclone 10 LP" device and generate ALTPLL IP in quartus 17.1. 

The software will generate a pll top level for me, and the intend_family is defined as "Cyclone 10 LP". 


In the verilog simulation model, this IP actually is instantiated from a general PLL module, and the instance name is pll2. 


Please check the generate condition section before the instance pll2. 

There is no condition matched for "Cyclone 10 LP", so no pll core is instantiated for device "Cyclone 10 LP". 

And I got unconnection on my pll top level. 


If you check the condition list, the family names are not in a good manner. 

I think you should review the family name list and double check if missing anything or making any redundency.  


I searched this issue for many days, but no helpfull feedback. 

I dont know how others fix this, or if anyone found this before. 



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3 Replies
Honored Contributor II

Have you raised a mysupport ticket?

Honored Contributor II


--- Quote Start ---  

Have you raised a mysupport ticket? 

--- Quote End ---  



Not yet. 

This is my first time to use altera fpga. 

Becasue our customer is asking for Cyclone, so we are moving our IP to that device. 


I will check the mysupport. 

Thanks for your information. 


Honored Contributor II



Please check the below link the problem has been addressed. 


Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)