ALTPLL will not get installed in Platform Builder

[SeanAB]

Quartus Prime Lite 24.1 on Windows

1. I am able to add ALTPLL as a component to blank project without issue. The wizard builds the files no problem. I was able to do the basic blink mux counter project.

2.  Platform Designer is another story. When attempting to add ALTPLL via Platform Designer, click Finish in the Wizard and the component gets cleared out. 

In version 23.1 there was a fatal error per this message: Why do I get a fatal error when creating an ALTPLL IP? Now, there is no error, just nothing.

Is there a work around?

[SeanAB]

Can confirm that the wizard installs the ALTPLL in Platform Designer in Linux.  

I found this older post that is exactly what I am seeing: fpga - Problem in adding IP to Platform Designer - Electrical Engineering Stack Exchange

[KennyTan_Altera]

Can you try on 25.1.1 quartus that is just release? Also may I know which version of windows that you are using?

[KennyTan_Altera]

The previous KDB pointed is listed with a Fatal error, from your side, do you see any error message?

[SeanAB]

@KennyTan_Altera thank you for the response.

Replying to both responses:

1. I am using Quartus Prime Lite 24.1 for a MAX10 10M50 Evaluation Kit. Pro edition 25.1.1 is not possible.

2.  There is no error message. It just closes without adding the ATPLL

After implementing the fix shared in an older Stack Exchange post, the wizard completes successfully.

[KennyTan_Altera]

This is the soln you implement, right?

The issue is that qmegawiz command returns with status 1 which means "Cancel", so the tcl interprets the result as the user had clicked "Cancel" instead of "Finish". As a dirty hack I changed the following line

if { $status != 0 } {

to

if { $status != 0 && $status != 1} {

in ~/intelfpga_lite/20.1/ip/altera/sopc_builder_ip/altera_avalon_mega_common/sopc_mwizc.tcl

and it works. The "Cancel" button doesn't work after this of course but it's a far smaller issue.

[SeanAB]

@KennyTan_Altera 

That is correct. The path to the file in Quartus Primer Standard / Lite 24.1 is C:\intelFPGA_lite\24.1std\ip\altera\sopc_builder_ip\altera_avalon_mega_common. The line to modify is around line 1050.

[KennyTan_Altera]

Thanks for the information. We will now close this thread.