I have an interface with a 52MHz clock and is center-aligned SDR input. Under the section Source-Synchronous Inputs then under Input Clocks it suggests not using a PLL on the input clock for low-speed inputs. So what is considered "low-speed"?
As a side note, the resources on designing timing constraints are all over the place. It is extremely confusing to follow between all the different guides which almost leaves it to a guess and check methodology.
I am Farabi who will supporting your request.
If you are using center aligned SDR and input clock below 100MHz, this is consider as low speed input, and PLL might not able to compensate the output clock to source clock efficiently. For SDR implementation, It is recommended to connect the input clock to the input capture register directly to get the best source synchronous setup.