Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
15772 Discussions

AN433 Suggests not using a PLL for Low-Speed inputs. What is considered "low-speed".

brandonb
Beginner
128 Views

I have an interface with a 52MHz clock and is center-aligned SDR input.  Under the section Source-Synchronous Inputs then under Input Clocks it suggests not using a PLL on the input clock for low-speed inputs.  So what is considered "low-speed"?

As a side note, the resources on designing timing constraints are all over the place.  It is extremely confusing to follow between all the different guides which almost leaves it to a guess and check methodology. 

0 Kudos
1 Reply
Farabi
Employee
115 Views

Hello, 

 

I am Farabi who will supporting your request. 

If you are using center aligned SDR and input clock below 100MHz, this is consider as low speed input, and PLL might not able to compensate the output clock to source clock efficiently. For SDR implementation, It is recommended to connect the input clock to the input capture register directly to get the best source synchronous setup. 

 

best regards,
Farabi

Reply