AOC 13.1 Quartus compilation FAILED

[Altera_Forum]

Hi, 

I am using AOCL 13.1 to program a Terasic DE5 board. I have installed Quartus 13.1 as well as AOCL 13.1 and the drivers on 64-bit Win7 with 8GB RAM. I compiled the Vector_add example. During the compilation process, I get the following error: "Quartus compilation FAILED".  And the log file shows the following errors:  Error: Hard Reset Controller can not be enabled for protocol mode 'pipe_g2' on node 'system:system_inst|system_acl_iface:acl_iface|altpcie_sv_hip_avmm_hwtcl:pcie|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip'. Use of the Hard Reset Controller at Gen2 data rates requires special considerations. If your design uses Autonomous HIP or CvP functionality at Gen2 data rates, please contact Altera for more information. If not, please switch to the Soft Reset Controller.   Info: "hrdrstctrl_dis" is a legal value   Error (35052): Partition "system_acl_iface:acl_iface" has port "system:system_inst|system_acl_iface:acl_iface|reconfig_to_xcvr_reconfig_to_xcvr[0]" driven by a constant connected to the illegal node "system:system_inst|system_acl_iface:acl_iface|altpcie_sv_hip_avmm_hwtcl:pcie|altpcie_sv_hip_ast_hwtcl:altera_s5_a2p|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip".   What should I do regarding this issue?  Thanks.

[Altera_Forum]

I recommend contacting Terasic about this. It seems like there is something missing in their board package files. 

 Also as a heads up, to compile for a large Stratix V device you'll need more than 8GB of RAM. I recommend having 32GB or more installed on the host compiling the hardware.

[Altera_Forum]

I raised an SR ticket with Altera about this one when I hit this message. There is a (< 5% of parts) StratixV device problem with hw reset block and PCIe Core in x4 PCIe Gen 2 mode only. 

Quartus 13.0 didn't mind, but Quartus 13.1 refuses to fit this combination. See http://www.altera.com/support/kdb/solutions/rd07232013_512.html for details.  To flip to software reset core you need to hack the qsys input file, and then the generated output.

[Altera_Forum]

That's the culprit but as far as I know that workaround isn't enough for the OpenCL design flow. There is a different solution for OpenCL so I recommend working with Terasic on this since I suspect they are working on a OpenCL centric fix for the issue in their board package as I speak.

[Altera_Forum]

--- Quote Start ---  That's the culprit but as far as I know that workaround isn't enough for the OpenCL design flow. There is a different solution for OpenCL so I recommend working with Terasic on this since I suspect they are working on a OpenCL centric fix for the issue in their board package as I speak.  --- Quote End ---    Is this because of the CVP/partial reconfig support needed by OpenCL?

[Altera_Forum]

Yes that's correct, Terasic will need to update the board project to support the CvP feature used by OpenCL.