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Altera_Forum

Honored Contributor I

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04-24-2018
05:39 PM

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About My VHDL Task

Hi, as a beginner in VHDL, I like to hear comments and ideas from you.

I have a task to do, my lecturer sent me a code but I couldn't find out. This's the code. -- library ieee; use ieee.std_logic_1164.all; entity singen is port ( clk : in std_logic; q : out std_logic_vector(7 downto 0) ); end entity; architecture rtl of singen is type regtype IS array (0 to 15) of std_logic_vector(7 downto 0); signal reg : regtype := (X"00", X"18", X"2d", X"3b", X"40", X"3b", X"2d", X"18", X"00", X"e8", X"d3", X"c5", X"c0", X"c5", X"d3", X"e8"); signal c : integer range 0 to 15 := 0; begin process begin wait until rising_edge(clk); if (c < 15) then c <= c + 1; else c <= 0; end if; end process; q <= reg(c); end rtl; -- He told me that "Use this file as component in VHDL and create design, where two sinusoidal signals with different frequencies (31250 Hz and 78125 Hz) are summed or subtracted (depending on outside signal)." With this above code how to generate two signals with different frequencies. It's generating only one signal and it's being q. But I don't know how he adjusted its frequency like he desired. Do you guys mind if explaining me? Thanks in advance.Link Copied

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Altera_Forum

Honored Contributor I

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04-24-2018
09:20 PM

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Do you remember your ;ecturer telling you about adders? hlw about prescalers? Clock frequencies?

Altera_Forum

Honored Contributor I

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04-25-2018
06:25 AM

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Altera_Forum

Honored Contributor I

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04-25-2018
07:18 AM

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Altera_Forum

Honored Contributor I

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04-25-2018
10:31 AM

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Altera_Forum

Honored Contributor I

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04-25-2018
04:11 PM

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Altera_Forum

Honored Contributor I

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04-25-2018
04:33 PM

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Altera_Forum

Honored Contributor I

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05-13-2018
02:22 AM

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huytergen,

You can't do what he asks using the code he sent you. It looks like the reg table is a simple 16 element full sine wave in twos-compliment with an amplitude of 64. You should research DDS (Direct Digital Synthesis) and will find alot of info on the web. The output frequency of a DDS is set by setting a "tuning word" to an appropriate value: F = M * Fc / 2^n where F is the sine wave frequency, Fc is the clock frequency, M is the tuning word, and n is the width of the phase accumulator in bits. Normally, the phase accumulator is much wider than the lookup table in order to get the desired frequency resolution. For example, if your clock is 100 Mhz and you want a resolution of 1 Hz, set M to 1 to find 2^n of 10.0e8 so you need n = 27. Most people would just use 32 bit for the phase accumulator and M. Then use the upper 4-bits as an index into your lookup table. So you will need to change his code to have a phase increment M input into the entity. The way he is incrementing c is very clumsy. It is going from 0 to 15 so it makes much more sense to make it an unsigned 4-bit number that you increment by M in one-line of code. M will also be an unsigned 4-bit number. He has M hardwired to 1, so the output frequency is fixed. In practice, you probably cannot achieve the desires frequencies with a 4-bit phase accumulator and will have to make it much wider. You can figure out the rest.
Altera_Forum

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05-13-2018
07:31 AM

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Altera_Forum

Honored Contributor I

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05-13-2018
11:35 PM

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