Accessing SDRAM Controller in Platform Designer from Verilog module through Avalon-MM interface

[Star_night2001]

Greetings there, I am currently working on an image processing project using the DE1-SoC FPGA and is totally new to this.

My current project framework consisting of

1. A customized Verilog submodule that basically receives and writes out an N-bit pixel data to memory (which I hope is SDRAM) every clock edge.
2. A Platform Designer system, mainly connecting the Nios II processor with the SDRAM Controller IP and an Avalon-MM interface (the Avalon MM Master Translator IP).

3. I have connected 1 & 2 in a Verilog top-level module through module instantiation. In order to establish the data streaming between custom module in part 1 and SDRAM controller in part 2, I have connected the SDRAM controller as the Avalon-MM slave and exported the Avalon-MM master port to be connected to my customized module. In the module, I have designed an FSM to manage the read, process and write to the Avalon interface.

I can read and write data into the SDRAM using C code in the Nios II Eclipse. However, the FSM is not working, and what I found out is that the waitrequest from the SDRAM is always HIGH, which indicates that the SDRAM might not be ready for transaction. My main problem now is that I cannot access the SDRAM from Quartus Verilog module.

Is here anyone who have experience in using DE1-SoC SDRAM and Avalon interface? I have attached a screenshot for my system design in Platform Designer, my top-level (qsys_lab.v) and sub-level (HistogramEqualization_MM.v) Verilog module, including the Avalon-MM FSM, and the state diagram of the FSM. I really appreciate for all the help, thank you!System Design in Platform DesignerRTL netlist viewerFSM State Machine

[RichardTanSY_Intel]

This design look very familiar with the design from Terasic. Is your design from Terasic?

Terasic User Guide: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=234&No=1021&PartNo=4#contents

You may refer to the example design and cross check with your design. (Note that you need Quartus Lite Edition to open the .par design file)

https://www.intel.com/content/www/us/en/design-example/715013/intel-max-10-fpga-sdram-rtl-design-example-terasic-de10-lite-board.html

You may contact Terasic Support  for further support or modification.

Regards,

Richard Tan

[RichardTanSY_Intel]

Hi,

Any update on this?

Do you able to resolve your issue?

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

The community users will be able to help you on your follow-up questions.

Thank you for reaching out to us!

Best Regards,

Richard Tan