Accessing SRAM from NIOS and Verilog Module

[Altera_Forum]

Hi, 

 I have implemented the Web Server example on the DE2-115 and modified it a bit to send data over ethernet to the DE2-115 board and store it in the SRAM. This data is around 1Mbit . Next I want to send this data to the GPIO headers of the DE2-115 on a trigger signal. I want to send the data on the rising edge of the clock signal I recieve on SMA CLKIN. All I need for this is a simple verilog code that transfers data from SRAM to the GPIO pins. The SRAM is accessed by the NIOS processor but I want to use hardware to transfer data from the SRAM to the pins since I want a faster transfer rate than NIOS can achieve. Do I need to use SGDMA or is there a simpler solution for this? Any help would be appreciated. Thanks!

[Altera_Forum]

Yeah you should use SGDMA to transfer your data to SDRAM. Look up Modular SGDMA. There are a lot of threads and examples on this forum on how to use this SGDMA. You still need the nios to write descriptors to the SGDMA, but the actually data transfer is no handled by the NIOS so it is much faster.

[Altera_Forum]

Hi Kraser, 

 Thanks for the reply. As I understand it, I am already using SGDMA to transfer data to the SRAM. So you mean I need to use it again to transfer data from SRAM to the GPIO pins (and HSMC pins) on the DE2-115? And to finally add this code (where the trigger starts data transfer) , do I need to add a Qsys component to connect to the SGDMA? It would be great if you could refer me to some instructive example you know of. Thanks!

[Altera_Forum]

SGDMA IP might consume quite lots of resources and overkill for your simple requirement. If you're willing to spend some time studying avalon specification, it will be easy to build a custom GPIO module with avalon-mm master interface. Here's avalon specification https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf

[Altera_Forum]

Hi Mini@nB, 

 Thanks for the suggestion. I went through the document regarding Avalon interfaces. So as I understand, I should create a GPIO module that does a master read operation of the SRAM and the output is produced on the GPIO pins at every clock cycle. I am assuming I need to modify the Avalon Memory-Mapped Master Template provided by Altera. And once I have a module I can add it to my Qsys system. I have two very basic questions. First, since I want to transfer data really fast from the SRAM to the GPIO(which are in turn connected to DDS boards) I would like to use an external clock. This will be connected to SMA CLKIN. So I am guessing I will need to include SMA CLKIN in my Qsys system as well. Am I on the right line of thought? Also, do I need to make any changes to the SRAM to make it accessible to both the NIOS processor (which stores data coming over ethernet to the SRAM) and the GPIO pins. I am sorry if these questions are really silly or not structured well. I can elaborate more on my application if you want. Thanks!

[Altera_Forum]

The external clock and GPIO pins need to be exported out of Qsys system by declaring them as conduit interface in the spec. If SRAM is Avalon-mm slave, you just plug and play the master (make the connection) and the Avalon fabric will do the rest for you. One more thing you have to include an additional Avalon-mm slave control interface in your module that instruct how/when to transfer data from the memory.

[Altera_Forum]

Hi Mini@nB, 

 Thanks for the help. I have looked at the pdf you suggested and have a rough idea of what should be done. But I still don't know how I have to do it. Do you know of any example I can follow where something is exported from the Qsys system and used in a verilog module outside the system (for instance in an always block in the top level module). For starters I thought of blinking an LED from a verilog script instead of the NIOS system. It would be great if you could refer me to some example or manual that explains how something like this is done. I'm sorry if this is an extremely trivial task and my question sounds stupid. Thanks again!

[Altera_Forum]

Here are couple of Avalon templates that you can make use of them 

For master,  https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html For slave, https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-memory-slave.html

[Altera_Forum]

Thanks for the links!  

So I used the custom master template and added it to my Qsys system. The user and control conduits are exported and so is the clock. The master is connected to the SRAM slave. As I understand it, I now instantiate this Qsys system in my top level verilog module and I can read out the data from 'user_read_buffer'. This doesn't seem to work when I try to display the data on to the LEDs. Is there something else I need to take care of when sharing the SRAM between NIOS and the hardware?

[Altera_Forum]

Dear Mini@nB, 

 I used the memory mapped master template as you suggested. I didn't make any changes to it since for a simple operation like mine it seemed to have the right control and user signals. I connected this master to the SRAM slave. Now from the documentation of the master template, the control_go is used to start reading from the slave. So what I do is use NIOS to write data to the SRAM (starting from address 0 ). Once this is done I use a switch to assert control_go. My control_read_base is the address the SRAM has on my Qsys window. control_fixed location is set to zero. I have set an LED to control_done. Now my question is that do I need to do something from NIOS to transfer the command to the custom module? Because when I store data on to the SRAM (say 1:1000 ) I expect to output the data on the LEDs as a pattern when I turn on a switch (and assert control_go). Is there something I am missing out? Thanks!